ATMEGA161L-4AI Atmel, ATMEGA161L-4AI Datasheet - Page 88

IC AVR MCU 16K LV 4MZ IND 44TQFP

ATMEGA161L-4AI

Manufacturer Part Number
ATMEGA161L-4AI
Description
IC AVR MCU 16K LV 4MZ IND 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet

Specifications of ATMEGA161L-4AI

Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Other names
ATMEGA161L4AI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA161L-4AI
Manufacturer:
Atmel
Quantity:
10 000
Using the External
Memory Interface
88
ATmega161(L)
The interface consists of:
Port A: multiplexed low-order address bus and data bus
Port C: high-order address bus
The ALE pin: address latch enable
The RD and WR pin: read and write strobes
The external memory interface is enabled by setting the external SRAM enable bit
(SRE) of the MCU Control Register (MCUCR) and will override the setting of the Data
Direction Registers DDRA, DDRD and DDRE. When the SRE bit is cleared (zero), the
external memory interface is disabled and the normal pin and data direction settings are
used. When SRE is low, the address space above the internal SRAM boundary is not
mapped into the internal SRAM, as in AVR parts do not have an external memory
interface.
When ALE goes from high to low, there is a valid address on Port A. ALE is low during a
data transfer. RD and WR are active when accessing the external memory only.
When the external memory interface is enabled, the ALE signal may have short pulses
when accessing the internal RAM, but the ALE signal is stable when accessing the
external memory.
Figure 54 sketches how to connect an external SRAM to the AVR using eight latches
that are transparent when G is high.
Figure 54. External SRAM Connected to the AVR
For details on the timing for the SRAM interface, please see Figure 83 through Figure 86
and Table 51 through Table 58.
AVR
Port C
Port A
ALE
WR
RD
D
G
Q
D[7:0]
A[15:8]
A[7:0]
RD
WR
SRAM
1228D–AVR–02/07

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