ATMEGA8L-8PC Atmel, ATMEGA8L-8PC Datasheet - Page 168

• Manufacturer Part Number: ATMEGA8L-8PC
• Description: IC AVR MCU 8K LV 8MHZ COM 28-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA8L8PC

Using the TWI
Figure 77. Interfacing the Application to the TWI in a Typical Transmission
168
writes to TWCR to
TWI bus
transmission of
ATmega8(L)
1. Application
START condition sent
Status code indicates
START
initiate
2. TWINT set.
START
TWDR, and loads appropriate control
3. Check TWSR to see if START was
• Bits 7..1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus.
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like
reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,
the application software is free to carry on other operations during a TWI byte transfer. Note that
the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in
SREG allow the application to decide whether or not assertion of the TWINT Flag should gener-
ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in
order to detect actions on the TWI bus.
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current
state of the TWI bus. The application software can then decide how the TWI should behave in
the next TWI bus cycle by manipulating the TWCR and TWDR Registers.
Figure 77
example, a Master wishes to transmit a single data byte to a Slave. This description is quite
abstract, a more detailed explanation follows later in this section. A simple code example imple-
menting the desired behavior is also presented.
sent. Application loads SLA+W into
signals into TWCR, makin sure that
1. The first step in a TWI transmission is to transmit a START condition. This is done by
2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and
and TWSTA is written to zero.
TWINT is written to one,
writing a specific value into TWCR, instructing the TWI hardware to transmit a START
condition. Which value to write is described later on. However, it is important that the
TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will
not start any operation as long as the TWINT bit in TWCR is set. Immediately after the
application has cleared TWINT, the TWI will initiate transmission of the START condition
TWSR is updated with a status code indicating that the START condition has success-
fully been sent
is a simple example of how the application can interface to the TWI hardware. In this
SLA+W
Status code indicates
SLA+W sent, ACK
4. TWINT set.
received
A
Application loads data into TWDR, and
5. Check TWSR to see if SLA+W was
loads appropriate control signals into
TWCR, making sure that TWINT is
sent and ACK received.
written to one
Data
data sent, ACK received
Status code indicates
6. TWINT set.
A
making sure that TWINT is written to one
7. Check TWSR to see if data was sent
Application loads appropriate control
signals to send STOP into TWCR,
STOP
and ACK received.
TWINT set
Indicates
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