PIC18C242-E/SO Microchip Technology, PIC18C242-E/SO Datasheet - Page 298

• Manufacturer Part Number: PIC18C242-E/SO
• Description: IC MCU OTP 8KX16 A/D 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C242E/SO

PIC18CXX2
S
SCI. See USART.
SCK .................................................................................. 121
SDI ................................................................................... 121
SDO ................................................................................. 121
Serial Clock, SCK ............................................................. 121
Serial Communication Interface. See USART
Serial Data In, SDI ........................................................... 121
Serial Data Out, SDO ....................................................... 121
Serial Peripheral Interface. See SPI
SETF ................................................................................ 221
Slave Select Synchronization ........................................... 125
Slave Select, SS .............................................................. 121
SLEEP .............................................................. 179, 185, 222
Software Simulator (MPLAB SIM) .................................... 230
Special Event Trigger. See Compare
Special Features of the CPU ............................................ 179
Special Function Registers ................................................ 42
SPI
SPI Master/Slave Connection .......................................... 123
SPI Module
SS .................................................................................... 121
SSP .................................................................................. 115
SSP Module
SSPCON1 Register .......................................................... 118
SSPOV ............................................................................. 139
SSPSTAT Register .......................................................... 116
STATUS Register ............................................................... 52
STKPTR Register ............................................................... 38
SUBFWB .......................................................................... 222
SUBLW ............................................................................ 223
SUBWF ............................................................................ 223
SUBWFB .......................................................................... 224
SWAPF ............................................................................ 224
Synchronous Serial Port. See SSP.
DS39026C-page 296
Configuration Registers ................................... 180–182
Map ............................................................................ 45
Master Mode ............................................................ 124
Serial Clock .............................................................. 121
Serial Data In ........................................................... 121
Serial Data Out ........................................................ 121
Slave Select ............................................................. 121
SPI Clock ................................................................. 124
SPI Mode ................................................................. 121
Master/Slave Connection ......................................... 123
Slave Mode .............................................................. 125
Slave Select Synchronization .................................. 125
Slave Synch Timing ................................................. 125
Slave Timing with CKE = 0 ...................................... 126
Slave Timing with CKE = 1 ...................................... 126
Block Diagram (SPI Mode) ...................................... 121
I
SPI Mode ................................................................. 121
SPI Mode. See SPI.
SSPBUF ................................................................... 124
SSPCON1 ................................................................ 118
SSPCON2 Register ................................................. 120
SSPSR ..................................................................... 124
SSPSTAT ................................................................. 116
TMR2 Output for Clock Shift ............................ 101, 102
SPI Master Mode ..................................................... 124
SPI Master./Slave Connection ................................. 123
SPI Slave Mode ....................................................... 125
R/W Bit ..................................................................... 129
2
C Mode. See I
Associated Registers ....................................... 127
Block Diagram .................................................. 121
2
C.
T
TABLAT Register ............................................................... 57
Table Pointer Operations (Table) ...................................... 57
Table Read Operation, Diagram ........................................ 55
Table Write Operation, Diagram ........................................ 55
TBLPTR Register ............................................................... 57
TBLRD ............................................................................. 225
TBLWT ............................................................................. 226
Timer0 ................................................................................ 93
Timer1 ................................................................................ 97
Timer2 .............................................................................. 101
Timer3 .............................................................................. 103
Timing Diagrams
Clock Source Edge Select (T0SE Bit) ....................... 95
Clock Source Select (T0CS Bit) ................................. 95
Overflow Interrupt ...................................................... 95
Prescaler. See Prescaler, Timer0
T0CON Register ........................................................ 93
Timing Diagram ....................................................... 249
Block Diagram ........................................................... 98
Block Diagram (16-bit R/W Mode) ............................. 98
Oscillator .............................................. 97, 99, 103, 105
Overflow Interrupt ................................ 97, 99, 103, 105
Prescaler. .................................................................. 98
Special Event Trigger (CCP) ..................... 99, 105, 110
T1CON Register ........................................................ 97
Timing Diagram ....................................................... 249
TMR1H Register ................................................ 97, 103
TMR1L Register ................................................. 97, 103
Associated Registers ............................................... 102
Block Diagram ......................................................... 102
Postscaler. See Postscaler, Timer2.
PR2 Register ................................................... 101, 112
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ............................................... 101, 102
T2CON Register ...................................................... 101
TMR2 Register ......................................................... 101
TMR2 to PR2 Match Interrupt .................. 101, 102, 112
Associated Registers ............................................... 105
Block Diagram ......................................................... 104
Block Diagram (16-bit R/W Mode) ........................... 104
T3CON Register ...................................................... 103
Acknowledge Sequence Timing .............................. 142
Baud Rate Generator with Clock Arbitration ............ 136
BRG Reset Due to SDA Collision ............................ 146
Bus Collision
Bus Collision During a Repeated START
Bus Collision During a Repeated START
Bus Collision During a START Condition
Bus Collision During a STOP Condition .................. 148
Bus Collision for Transmit and Acknowledge .......... 144
I
I
I
I
Master Mode Transmit Clock Arbitration ................. 143
Repeat START Condition ........................................ 138
Slave Synchronization ............................................. 125
SPI Mode Timing (Master Mode) SPI Mode
SPI Mode Timing (Slave Mode with CKE = 0) ......... 126
SPI Mode Timing (Slave Mode with CKE = 1) ......... 126
2
2
2
2
C Bus Data ............................................................ 259
C Master Mode First START Bit Timing ................ 137
C Master Mode Reception Timing ......................... 141
C Master Mode Transmission Timing ................... 140
START Condition Timing ................................. 145
Condition (Case 1) ........................................... 147
Condition (Case2) ............................................ 147
(SCL = 0) ......................................................... 146
Master Mode Timing Diagram ......................... 124
2001 Microchip Technology Inc.