PIC18C242-E/SO Microchip Technology, PIC18C242-E/SO Datasheet - Page 39

• Manufacturer Part Number: PIC18C242-E/SO
• Description: IC MCU OTP 8KX16 A/D 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C242-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: MSSP, SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• For Use With: I3DB18C452 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C242E/SO

4.2
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is executed, or an interrupt
is acknowledged. The PC value is pulled off the stack
on a RETURN,
PCLATU and PCLATH are not affected by any of the call
or return instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all RESETS. There is no RAM associated
with stack pointer 00000b. This is only a RESET value.
During a CALL type instruction causing a push onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR is trans-
ferred to the PC and then the stack pointer is
decremented.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the address on the top of the stack is readable and writ-
able through SFR registers. Data can also be pushed
to, or popped from, the stack, using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at, or
beyond the 31 levels provided.
4.2.1
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
software stack, if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack opera-
tions..
2001 Microchip Technology Inc.
Return Address Stack
TOP-OF-STACK ACCESS
RETLW or a RETFIE instruction.
4.2.2
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full, depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. Refer to
Section 18.0 for a description of the device configura-
tion bits. If STVREN is set (default), the 31st push will
push the (PC + 2) value onto the stack, set the STKFUL
bit, and reset the device. The STKFUL bit will remain
set and the stack pointer will be set to 0.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software or a POR occurs.
Note:
Returning a value of zero to the PC on an
underflow, has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and appro-
priate actions can be taken.
RETURN STACK POINTER
(STKPTR)
PIC18CXX2
DS39026C-page 37