T89C51CC01CA-RLTIM Atmel, T89C51CC01CA-RLTIM Datasheet - Page 37
![IC 8051 MCU FLASH 32K 44VQFP](/photos/6/92/69202/313-44-vqfp_sml.jpg)
T89C51CC01CA-RLTIM
Manufacturer Part Number
T89C51CC01CA-RLTIM
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC01CA-7CTIM.pdf
(167 pages)
2.T89C51CC01CA-7CTIM.pdf
(12 pages)
3.T89C51CC01CA-7CTIM.pdf
(32 pages)
4.T89C51CC01CA-7CTIM.pdf
(29 pages)
Specifications of T89C51CC01CA-RLTIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC01CARLTIM
Available stocks
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- T89C51CC01CA-7CTIM PDF datasheet
- T89C51CC01CA-7CTIM PDF datasheet #2
- T89C51CC01CA-7CTIM PDF datasheet #3
- T89C51CC01CA-7CTIM PDF datasheet #4
- Current page: 37 of 167
- Download datasheet (2Mb)
Overview of FM0
Operations
Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column
Launching Programming
4129N–CAN–03/08
The CPU interfaces to the Flash memory through the FCON register and AUXR1
register.
These registers are used to:
•
•
•
latches space is made accessible by setting the FPS bit in FCON register. Writing is
possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a
page while bits 14 to 7 are used to select the programming address of the page.
Setting FPS bit takes precedence on the EXTRAM bit in AUXR register.
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-
dance with Table 25. A MOVC instruction is then used for reading these spaces.
Table 25. FM0 Blocks Select Bits
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5xh followed by Axh. Table 26 summarizes the memory
spaces to program according to FMOD1:0 bits.
Map the memory spaces in the adressable space
Launch the programming of the memory spaces
Get the status of the Flash memory (busy/not busy)
FMOD1
0
0
1
1
FMOD0
0
1
0
1
FM0 Adressable space
User (0000h-7FFFh)
Extra Row(FF80h-FFFFh)
Hardware Security Byte (0000h)
Reserved
37
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