T89C51RD2-SLSIM Atmel, T89C51RD2-SLSIM Datasheet - Page 55

• Manufacturer Part Number: T89C51RD2-SLSIM
• Description: IC MICRO CTRL 64K FLASH 44PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of T89C51RD2-SLSIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Boot Loader Lock Bit (BLLB)
Flash memory lock bits
4243G–8051–05/03
One bit of the HSB is used to secure by hardware the internal boot loader sector against
software reprogramming.
When the BLLB is cleared, any attempt to write in the boot loader segment (Address
FC00h to FFFFh) will have no effect. This protection applies for software writing only.
Boot Loader Jump Bit (BLJB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
•
•
The three lock bits provide different levels of protection for the on-chip code and data,
when programmed according to Table 29.
Number
SB
Bit
2-0
7
7
6
5
4
3
When this bit is set the boot address is 0000h.
When this bit is reset the boot address is FC03h. By default, this bit is cleared and
the ISP is enabled.
Mnemonic Description
BLJB
LB2-0
BLLB
BLJB
Bit
SB
6
-
-
Safe Bit
This bit must be cleared to secure the content of the HSB. Only security level can
be increased.
Boot loader Jump Bit
Set to force hardware boot address at 0000h. (unless previously force by hardware
conditions as described in the chapter 9.6).
Clear to force hardware boot address at FC03h (default).
Boot loader Lock Bit
Set to allow programming and writing of the boot loader segment.
Clear to forbid software programming and writing of the boot loader segment
(default). This protection protect only ISP or IAP access; protection through parallel
access is done globally by the lock bits LB2-0.
Reserved
Do not clear this bit.
Reserved
Do not clear this bit.
User Memory Lock Bits
See Table 29
BLLB
5
4
-
3
-
LB2
2
T89C51RD2
LB1
1
LB0
0
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