ATMEGA64-16MJ Atmel, ATMEGA64-16MJ Datasheet - Page 268

• Manufacturer Part Number: ATMEGA64-16MJ
• Description: IC MCU AVR 64K 5V 16MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64-16MJ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2490Q–AVR–06/10
Table 104. Boundary-scan Signals for the ADC
Note:
If the ADC is not to be used during scan, the recommended input values from
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
The AVR ADC is based on the analog circuitry shown in
mation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is
usually to ensure that an applied analog voltage is measured within some limits. This can easily
be done without running a successive approximation algorithm: apply the lower limit on the digi-
tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit
on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC needs not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following:
•
•
•
As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
Signal
Name
SCTEST
ST
VCCREN
The Port Pin for the ADC channel in use must be configured to be an input with pull-up
disabled to avoid signal contention.
In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
enabling the ADC. The user is advised to wait at least 200 ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
low (Sample mode).
1. Incorrect setting of the switches in
part. There are several input choices to the S&H circuitry on the negative input of the output
comparator in
gap reference source, or Ground.
Direction
as Seen
from the
ADC
Input
Input
Input
The lower limit is:
The upper limit is:
Figure
Description
Switch-cap TEST
enable. Output from
x10 gain stage send
out to Port Pin
having ADC_4
Output of gain
stages will settle
faster if this signal is
high first two ACLK
periods after
AMPEN goes high.
ACC reference
voltage.
Selects Vcc as the
134. Make sure only one path is selected from either one ADC pin, Band-
1024 1,5V 0,95 5V
1024 1,5V 1,05 5V
Figure 134
⋅
⋅
(1)
Recommended
Input when not
⋅
⋅
(Continued)
in Use
will make signal contention and may damage the
⁄
0
0
0
⁄
Figure 134
=
=
291
323
CC
Recommended Inputs
are Used, and CPU is
=
=
Output Values when
.
not Using the ADC
0x123
0x143
with a successive approxi-
ATmega64(L)
0
0
0
Table 104
should
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