ATMEGA64-16MJ Atmel, ATMEGA64-16MJ Datasheet - Page 305

no-image

ATMEGA64-16MJ

Manufacturer Part Number
ATMEGA64-16MJ
Description
IC MCU AVR 64K 5V 16MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64-16MJ

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Serial
Downloading
2490Q–AVR–06/10
Table 126. Parallel Programming Characteristics, V
Notes:
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface. Note that throughout the description about Serial downloading, MOSI and MISO
are used to describe the serial data in and serial data out, respectively. For ATmega64, these
pins are mapped to PDI and PDO.
Symbol
V
I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PP
DVXH
XLXH
XHXL
XLDX
XLWL
XLPH
PLXH
BVPH
PHPL
PLBX
WLBX
PLWL
BVWL
WLWH
WLRL
WLRH
WLRH_CE
XLOL
BVDV
OLDV
OHDZ
PP
1.
2. t
commands.
t
WLRH_CE
WLRH
Parameter
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
XTAL1 Low to PAGEL high
PAGEL low to XTAL1 high
BS1 Valid before PAGEL High
PAGEL Pulse Width High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
WR Low to RDY/BSY High
WR Low to RDY/BSY High for Chip Erase
XTAL1 Low to OE Low
BS1 Valid to DATA valid
OE Low to DATA Valid
OE High to DATA Tri-stated
is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock bits
is valid for the Chip Erase command.
(1)
(2)
CC
= 5V ±10%
11.5
Min
200
150
150
150
150
3.7
7.5
67
67
67
67
67
67
67
0
0
0
0
0
Table 127 on page
Typ
ATmega64(L)
Max
12.5
250
250
250
250
4.5
1
9
Units
ms
μA
ns
μs
ns
V
306, the pin
305

Related parts for ATMEGA64-16MJ