ATMEGA169V-8AI SL709 Atmel, ATMEGA169V-8AI SL709 Datasheet - Page 154

• Manufacturer Part Number: ATMEGA169V-8AI SL709
• Description: IC AVR MCU 16K 8MHZ 1.8V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169V-8AI SL709

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA169V8ASL709

Internal Clock Generation –
The Baud Rate Generator
154
ATmega169/V
Figure 70. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master
modes of operation. The description in this section refers to Figure 70.
The USART Baud Rate Register (UBRR) and the down-counter connected to it function
as a programmable prescaler or baud rate generator. The down-counter, running at sys-
tem clock (f
to zero or when the UBRRL Register is written. A clock is generated each time the
counter reaches zero. This clock is the baud rate generator clock output (=
f
16 depending on mode. The baud rate generator output is used directly by the
Receiver’s clock and data recovery units. However, the recovery units use a state
machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSEL,
U2X and DDR_XCK bits.
Table 71 contains equations for calculating the baud rate (in bits per second) and for
calculating the UBRR value for each mode of operation using an internally generated
clock source.
osc
txclk
rxclk
xcki
xcko
fosc
/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or
DDR_XCK
XCK
Pin
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
XTAL pin frequency (System Clock).
osc
xcko
xcki
), is loaded with the UBRR value each time the counter has counted down
OSC
Down-Counter
Prescaling
Register
UBRR
Sync
UBRR+1
fosc
Detector
UCPOL
Edge
/2
/4
/2
DDR_XCK
U2X
0
1
0
1
2514P–AVR–07/06
0
1
1
0
UMSEL
txclk
rxclk