ATMEGA169V-8AI SL709 Atmel, ATMEGA169V-8AI SL709 Datasheet - Page 155

• Manufacturer Part Number: ATMEGA169V-8AI SL709
• Description: IC AVR MCU 16K 8MHZ 1.8V 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169V-8AI SL709

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ATMEGA169V8ASL709

Double Speed Operation
(U2X)
External Clock
2514P–AVR–07/06
Table 71. Equations for Calculating Baud Rate Register Setting
Note:
Some examples of UBRR values for some system clock frequencies are found in Table
79 (see page 175).
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only
has effect for the asynchronous operation. Set this bit to zero when using synchronous
operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively
doubling the transfer rate for asynchronous communication. Note however that the
Receiver will in this case only use half the number of samples (reduced from 16 to 8) for
data sampling and clock recovery, and therefore a more accurate baud rate setting and
system clock are required when this mode is used. For the Transmitter, there are no
downsides.
External clocking is used by the synchronous slave modes of operation. The description
in this section refers to Figure 70 for details.
External clock input from the XCK pin is sampled by a synchronization register to mini-
mize the chance of meta-stability. The output from the synchronization register must
then pass through an edge detector before it can be used by the Transmitter and
Receiver. This process introduces a two CPU clock period delay and therefore the max-
imum external XCK clock frequency is limited by the following equation:
Note that f
mended to add some margin to avoid possible loss of data due to frequency variations.
Operating Mode
Asynchronous Normal
mode (U2X = 0)
Asynchronous Double
Speed mode (U2X = 1)
Synchronous Master
mode
BAUD Baud rate (in bits per second, bps)
f
UBRR Contents of the UBRRH and UBRRL Registers, (0-4095)
OSC
1. The baud rate is defined to be the transfer rate in bit per second (bps)
System Oscillator clock frequency
osc
depends on the stability of the system clock source. It is therefore recom-
BAUD
BAUD
BAUD
Equation for Calculating
Baud Rate
=
=
=
-------------------------------------- -
16 UBRR
f
---------------------------------- -
8 UBRR
---------------------------------- -
2 UBRR
XCK
(
(
(
f
f
f
<
OSC
OSC
OSC
(1)
f
---------- -
OSC
4
+
+
+
1
1
1
)
)
)
Equation for Calculating
UBRR
ATmega169/V
UBRR
UBRR
UBRR Value
=
=
=
----------------------- - 1
16BAUD
------------------- - 1
8BAUD
------------------- - 1
2BAUD
f
f
f
OSC
OSC
OSC
–
–
–
155