DSPIC30F6011A-20I/PT Microchip Technology, DSPIC30F6011A-20I/PT Datasheet
DSPIC30F6011A-20I/PT
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DSPIC30F6011A-20I/PT Summary of contents
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... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70143E ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... All DSP instructions are single cycle: - Multiply-Accumulate (MAC) operation • Single-cycle ±16 shift © 2011 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...
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... CMOS Technology: • Low-power, high-speed Flash technology • Wide operating voltage range (2.5V to 5.5V) • Industrial and Extended temperature ranges • Low power consumption dsPIC30F6011A/6012A/6013A/6014A Controller Families Program Memory Device Pins Bytes Instructions dsPIC30F6011A 64 132K 44K dsPIC30F6012A 64 144K 48K dsPIC30F6013A ...
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... TQFP RG15 1 T2CK/RC1 2 T3CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF © 2011 Microchip Technology Inc. 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F6011A 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 DS70143E-page 5 ...
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... Pin Diagrams (Continued) 64-Pin TQFP COFS/RG15 1 T2CK/RC1 2 T3CK/RC2 3 SCK2/CN8/RG6 4 SDI2/CN9/RG7 5 SDO2/CN10/RG8 6 MCLR 7 SS2/CN11/RG9 AN5/IC8/CN7/RB5 11 AN4/IC7/CN6/RB4 12 AN3/CN5/RB3 13 AN2/SS1/LVDIN/CN4/RB2 14 AN1/V -/CN3/RB1 15 REF AN0/V +/CN2/RB0 16 REF DS70143E-page 6 48 EMUC1/SOSCO/T1CK/CN0/RC14 47 EMUD1/SOSCI/T4CK/CN1/RC13 46 EMUC2/OC1/RD0 45 IC4/INT4/RD11 44 IC3/INT3/RD10 43 IC2/INT2/RD9 42 IC1/INT1/RD8 dsPIC30F6012A 40 OSC2/CLKO/RC15 39 OSC1/CLKI SCL/RG2 36 SDA/RG3 35 EMUC3/SCK1/INT0/RF6 34 U1RX/SDI1/RF2 33 EMUD3/U1TX/SDO1/RF3 ...
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... Pin Diagrams (Continued) 80-Pin TQFP 1 RG15 T2CK/RC1 2 3 T3CK/RC2 4 T4CK/RC3 T5CK/RC4 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 © 2011 Microchip Technology Inc dsPIC30F6013A EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS ...
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... Pin Diagrams (Continued) 80-Pin TQFP 1 COFS/RG15 T2CK/RC1 2 3 T3CK/RC2 4 T4CK/RC3 T5CK/RC4 5 SCK2/CN8/RG6 6 SDI2/CN9/RG7 7 SDO2/CN10/RG8 8 MCLR 9 SS2/CN11/RG9 INT1/RA12 13 INT2/RA13 14 AN5/CN7/RB5 15 AN4/CN6/RB4 16 AN3/CN5/RB3 17 AN2/SS1/LVDIN/CN4/RB2 18 PGC/EMUC/AN1/CN3/RB1 19 PGD/EMUD/AN0/CN2/RB0 20 DS70143E-page dsPIC30F6014A EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 EMUC2/OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 V SS OSC2/CLKO/RC15 OSC1/CLKI V DD SCL/RG2 ...
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... Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 CPU Architecture Overview........................................................................................................................................................ 17 3.0 Memory Organization ................................................................................................................................................................. 25 4.0 Address Generator Units............................................................................................................................................................ 39 5.0 Interrupts .................................................................................................................................................................................... 45 6.0 Flash Program Memory.............................................................................................................................................................. 51 7.0 Data EEPROM Memory ............................................................................................................................................................. 57 8.0 I/O Ports ..................................................................................................................................................................................... 61 9.0 Timer1 Module ........................................................................................................................................................................... 67 10.0 Timer2/3 Module ........................................................................................................................................................................ 71 11.0 Timer4/5 Module ....................................................................................................................................................................... 77 12.0 Input Capture Module................................................................................................................................................................. 81 13.0 Output Compare Module ............................................................................................................................................................ 85 14.0 SPI™ ...
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... NOTES: DS70143E-page 10 © 2011 Microchip Technology Inc. ...
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... Controller (DSC) devices. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) func- tionality within a high-performance microcontroller (MCU) architecture. Figure 1-2 show device block dsPIC30F6011A/6012A and dsPIC30F6013A/6014A, respectively. © 2011 Microchip Technology Inc. Manual” 16-bit Figure 1-1 and diagrams for DS70143E-page 11 ...
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... FIGURE 1-1: dsPIC30F6011A/6012A BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCU Program Counter Stack Address Latch Control Logic Program Memory (Up to 144 Kbytes) Data EEPROM ( Kbytes) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...
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... FIGURE 1-2: dsPIC30F6013A/6014A BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCH PCU Program Counter Stack Address Latch Control Logic Program Memory (Up to 144 Kbytes) Data EEPROM ( Kbytes) 16 Data Latch ROM Latch 24 16 Instruction Decode & ...
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... Table 1-1 provides a brief description of device I/O pin- outs and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...
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... TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type PGD I/O ST In-Circuit Serial Programming™ data input/output pin. PGC I ST In-Circuit Serial Programming clock input pin. RA6-RA7 I/O ST PORTA is a bidirectional I/O port. RA9-RA10 I/O ST RA12-RA15 I/O ...
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... NOTES: DS70143E-page 16 © 2011 Microchip Technology Inc. ...
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... CPU ARCHITECTURE OVERVIEW Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
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... The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors ...
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... FIGURE 2-1: PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset ...
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... Divide Support The dsPIC DSC devices feature a 16/16-bit signed fractional divide operation, as well as 32/16-bit and 16/ 16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides. The following instructions and data sizes are supported: • DIVF - 16/16 signed fractional divide • ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2011 Microchip Technology Inc. 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70143E-page 21 ...
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... MULTIPLIER The 17 x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the mul- tiplier input value ...
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... The SA and SB bits are modified each time data passes through the adder/subtracter but can only be cleared by the user. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When satu- ...
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... Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space may also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 frac- tional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder ...
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... MEMORY ORGANIZATION Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
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... FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F6011A/ 6013A Reset – GOTO Instruction Reset – Target Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (44K instructions) Reserved (Read ‘0’s) Data EEPROM (2 Kbytes) Reserved UNITID (32 instr.) ...
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... TABLE 3-1: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User User TBLRD/TBLWT (TBLPAG<7> Configuration TBLRD/TBLWT (TBLPAG<7> Program Space Visibility User FIGURE 3-3: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Using Program 0 Counter Using Program 0 Space Visibility Using ...
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... DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS This architecture fetches 24-bit wide program memory. Consequently, instructions are always However, as the architecture is modified Harvard, data can also be present in program space. There are two methods by which program space can be accessed: via special table instructions, or through ...
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... FIGURE 3-5: PROGRAM DATA TABLE ACCESS (MSB) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 00000000 0x000006 Program Memory ‘Phantom’ Byte (read as ‘0’) 3.1.2 DATA ACCESS FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word program space page ...
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... FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space 15 EA<15> Data Space 15 EA EA<15> Upper Half of Data Space is Mapped into Program Space BSET CORCON,#2 ; PSV bit set MOV #0x02 Set PSVPAG register MOV W0, PSVPAG MOV 0x8000 Access program memory location ...
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... Data Address Space The core has two data spaces. The data spaces can be considered either separate (for some DSP instruc- tions one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths ...
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... FIGURE 3-7: DATA SPACE MEMORY MAP FOR dsPIC30F6011A/6013A MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 6 Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70143E-page 32 LSB 16 bits Address MSB LSB 0x0000 SFR Space ...
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... FIGURE 3-8: DATA SPACE MEMORY MAP FOR dsPIC30F6012A/6014A MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 8 Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2011 Microchip Technology Inc. LSB 16 bits Address MSB ...
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... FIGURE 3-9: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read) Indirect EA from any W TABLE 3-2: EFFECT OF INVALID MEMORY ACCESSES Attempted Operation Data Returned unimplemented address used to access Y data space in a MAC instruction ...
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... All word accesses must be aligned to an even address. Misaligned word data fetches are not supported so care must be taken when mixing byte and word opera- tions, or translating from 8-bit MCU code. Should a mis- aligned read or write be attempted, an address error trap will be generated. If the error occurred on a read, ...
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... DATA RAM PROTECTION FEATURE The dsPIC30F6011A/6012A/6013A/6014A support data RAM protection features which enable segments of RAM to be protected when used in con- junction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. ...
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... Microchip Technology Inc. DS70143E-page 37 ...
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... DS70143E-page 38 © 2011 Microchip Technology Inc. ...
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... ADDRESS GENERATOR UNITS Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the Addressing modes supported by most MCU instruc- tions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...
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... START AND END ADDRESS The Modulo Addressing scheme requires that a start- ing and an ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT, YMODEND (see Note: Y space Modulo Addressing EA calcula- tions assume word sized data (LSb of every EA is always clear) ...
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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address calculation associated with any W register important to realize that the address boundaries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decre- menting buffers) boundary addresses (not just equal to) ...
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... FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 4096 ...
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... NOTES: DS70143E-page 44 © 2011 Microchip Technology Inc. ...
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... INTERRUPTS Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
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... C2 – Combined IRQ for CAN2 39-40 47-48 Reserved 41 49 DCI – Codec Transfer Done 42 50 LVD – Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority Note 1: Reserved on dsPIC30F6011A and dsPIC30F6013A because the DCI module is not available on these devices. © 2011 Microchip Technology Inc. (1) ...
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... Reset Sequence A Reset is not a true exception, because the interrupt controller is not involved in the Reset process. The pro- cessor initializes its registers in response to a Reset which forces the PC to zero. The processor then begins program execution at location 0x000000. A GOTO instruction is stored in the first program memory loca- tion immediately followed by the address target for the GOTO instruction ...
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... Execution of a “BRA #literal” instruction or a “GOTO #literal” instruction, where literal is an unimplemented program memory address • Executing instructions after modifying the PC to point to unimplemented program memory addresses. The PC may be modified by loading a value into the stack and executing a RETURN ...
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... FIGURE 5-2: INTERRUPT STACK FRAME 0x0000 15 0 W15 (before CALL) PC<15:0> SRL IPL3 PC<22:16> W15 (after CALL) <Free Word> POP : [--W15] PUSH: [W15++] Note 1: The user can always lower the priority level by writing a new value into SR. The Interrupt Service Routine must clear the ...
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... DS70143E-page 50 © 2011 Microchip Technology Inc. ...
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... FLASH PROGRAM MEMORY Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions or 96 bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the table pointer must be changed at each panel boundary ...
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... Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 2 msec in duration and the processor stalls (waits) until the oper- ation is finished. Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished ...
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... LOADING WRITE LATCHES Example 6-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer. EXAMPLE 6-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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... Microchip Technology Inc. DS70143E-page 55 ...
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... NOTES: DS70143E-page 56 © 2011 Microchip Technology Inc. ...
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... DATA EEPROM MEMORY Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
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... Erasing Data EEPROM 7.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM, and set the ERASE and WREN bits in the NVMCON register ...
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... Writing to the Data EEPROM To write an EEPROM data location, the following sequence must be followed: 1. Erase data EEPROM word. a) Select word, data EEPROM erase and set WREN bit in NVMCON register. b) Write address of word to be erased into NVMADR. c) Enable NVM interrupt (optional). ...
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... WRITING A BLOCK OF DATA EEPROM To write a block of data EEPROM, write to all sixteen latches first, then set the NVMCON register and program the block. EXAMPLE 7-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 TBLWTL W2 [ W0]++ , MOV ...
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... I/O PORTS Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). All of the device pins (except V ...
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... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (out- ...
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... Microchip Technology Inc. DS70143E-page 63 ...
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... DS70143E-page 64 © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. DS70143E-page 65 ...
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... Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 8-11: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F6011A/6012A (1) (BITS 7-0) SFR Addr. Bit 7 Bit 6 Name ...
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... TIMER1 MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This section describes the 16-bit General Purpose Timer1 module and associated operational modes ...
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... Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accumulation mode. This mode allows the internal T to increment the respective timer when the gate input signal (T1CK pin) is asserted high. Control bit TGATE (T1CON<6>) must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0) ...
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... RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the Period register and is then reset to ‘0’. The TSYNC bit must be asserted to a logic ‘0’ ...
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... DS70143E-page 70 © 2011 Microchip Technology Inc. ...
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... TIMER2/3 MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and gen- eral device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD Write TMR2 Read TMR2 16 Reset ADC Event Trigger Equal 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70143E-page 72 ...
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... FIGURE 10-2: 16-BIT TIMER2 BLOCK DIAGRAM Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2011 Microchip Technology Inc. PR2 Comparator x 16 TMR2 TGATE TON ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit TGATE (T2CON<6>) must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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... Microchip Technology Inc. DS70143E-page 75 ...
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... NOTES: DS70143E-page 76 © 2011 Microchip Technology Inc. ...
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... TIMER4/5 MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). This section describes the second 32-bit General Pur- pose Timer module (Timer4/5) and associated Opera- tional modes ...
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... Reset 0 T5IF Event Flag 1 TGATE T5CK Note: In the dsPIC30F6011A and dsPIC30F6012A devices, there is no T5CK pin. Therefore, in this device the following modes should not be used for Timer5: TCS = 1 (16-bit Counter) TCS = 0, TGATE = 1 (Gated Time Accumulation) DS70143E-page 78 PR4 Comparator x 16 TMR4 TGATE ...
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... Microchip Technology Inc. DS70143E-page 79 ...
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... NOTES: DS70143E-page 80 © 2011 Microchip Technology Inc. ...
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... INPUT CAPTURE MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). ...
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... CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBFNE – Input Capture Buffer Not Empty • ICOV – Input Capture Overflow ...
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... Microchip Technology Inc. DS70143E-page 83 ...
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... NOTES: DS70143E-page 84 © 2011 Microchip Technology Inc. ...
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... OUTPUT COMPARE MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). ...
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... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 13.2 Simple Output Compare Match Mode When control bits OCM< ...
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... PWM PERIOD The PWM period is specified by writing to the PRx register. The PWM period can be calculated using Equation 13-1. EQUATION 13-1: PWM period = [(PRx • 4 • T (TMRx prescale value) PWM frequency is defined as 1/[PWM period]. FIGURE 13-2: PWM OUTPUT TIMING ...
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... Output Compare Operation During CPU Sleep Mode When the CPU enters Sleep mode, all internal clocks are stopped. Therefore, when the CPU enters the Sleep state, the output compare channel will drive the pin to the active state that was observed prior to entering the CPU Sleep state ...
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... Microchip Technology Inc. DS70143E-page 89 ...
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... NOTES: DS70143E-page 90 © 2011 Microchip Technology Inc. ...
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... SPI™ MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). ...
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... Framed SPI Support The module supports a basic framed SPI protocol in Master or Slave mode. The control bit FRMEN enables framed SPI support and causes the SSx pin to perform the frame synchronization pulse (FSYNC) function. The control bit SPIFSD determines whether the SSx ...
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... Slave Select Synchronization The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode with SSx pin control enabled (SSEN = 1). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When SSx pin goes high, the SDOx pin is no longer driven ...
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... DS70143E-page 94 © 2011 Microchip Technology Inc. ...
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... I C™ MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). ...
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... FIGURE 15-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70143E-page 96 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control ...
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... I C Module Addresses The I2CADD register contains the Slave mode addresses. The register is a 10-bit register. If the A10M bit (I2CCON<10>) is ‘0’, the address is interpreted by the module as a 7-bit address. When an address is received compared to the 7 Least Significant bits of the I2CADD register. ...
Page 98
... MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 15.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated ...
Page 99
... Interrupts 2 The I C module generates two interrupt flags, MI2CIF Master Interrupt Flag) and SI2CIF (I rupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. 15.8 Slope Control ...
Page 100
... BAUD RATE GENERATOR Master mode, the reload value for the BRG is located in the I2CBRG register. When the BRG is loaded with this value, the BRG counts down to ‘0’ and stops until another reload has taken place. If clock arbi- tration is taking place, for instance, the BRG is reloaded when the SCL pin is sampled high ...
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... Microchip Technology Inc. DS70143E-page 101 ...
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... NOTES: DS70143E-page 102 © 2011 Microchip Technology Inc. ...
Page 103
... UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” ...
Page 104
... FIGURE 16-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70143E-page 104 Internal Data Bus 16 Read Write URX8 UxRXREG Low Byte Receive Buffer Control ...
Page 105
... Enabling and Setting Up UART 16.2.1 ENABLING THE UART The UART module is enabled by setting the UARTEN bit in the UxMODE register (where 2). Once enabled, the UxTX and UxRX pins are configured as an output and an input respectively, overriding the TRIS and LATCH register bit settings for the corresponding I/O port pins. The UxTX pin is at logic ‘ ...
Page 106
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...
Page 107
... FRAMING ERROR (FERR) The FERR bit (UxSTA<2>) is set if a ‘0’ is detected instead of a Stop bit. If two Stop bits are selected, both Stop bits must be ‘1’, otherwise FERR will be set. The read only FERR bit is buffered along with the received data ...
Page 108
... Auto-Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a capture input (IC1 for UART1, IC2 for UART2). To enable this mode, the user must program the input cap- ture module to detect the falling and rising edges of the Start bit ...
Page 109
... Microchip Technology Inc. DS70143E-page 109 ...
Page 110
... NOTES: DS70143E-page 110 © 2011 Microchip Technology Inc. ...
Page 111
... CAN MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). 17.1 ...
Page 112
... FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFERS TXB0 TXB1 Message Queue Control Transmit Byte Sequencer PROTOCOL ENGINE Transmit Logic (1) CiTX Note refers to a particular CAN module (CAN1 or CAN2). DS70143E-page 112 Acceptance Mask TXB2 RXM0 A Acceptance Filter c RXF0 ...
Page 113
... Modes of Operation The CAN module can operate in one of several Operation modes selected by the user. These modes include: • Initialization Mode • Disable Mode • Normal Operation Mode • Listen Only Mode • Loopback Mode • Error Recognition Mode Modes are requested by setting the REQOP<2:0> bits (CiCTRL< ...
Page 114
... Message Reception 17.4.1 RECEIVE BUFFERS The CAN bus module has 3 receive buffers. However, one of the receive buffers is always committed to mon- itoring the bus for incoming messages. This buffer is called the Message Assembly Buffer (MAB). So there are 2 receive buffers visible, RXB0 and RXB1, that can ...
Page 115
... Receive Error Interrupts: A receive error interrupt will be indicated by the ERRIF bit. This bit shows that an error condition occurred. The source of the error can be deter- mined by checking the bits in the CAN Interrupt status register, CiINTF. - Invalid Message Received: If any type of error occurred during reception of the last message, an error will be indicated by the IVRIF bit ...
Page 116
... TRANSMIT INTERRUPTS Transmit interrupts can be divided into 2 major groups, each including various conditions that generate interrupts: • Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. Reading the TXnIF flags will indicate which transmit buffer is available and caused the interrupt. • ...
Page 117
... PRESCALER SETTING There is a programmable prescaler with integral values ranging from 1 to 64, in addition to a fixed divide-by-2 for clock generation. The time quantum (T unit of time derived from the oscillator period, and is given by Equation 17-1. Note: F must not exceed 30 MHz. If ...
Page 118
... DS70143E-page 118 © 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. DS70143E-page 119 ...
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... DS70143E-page 120 © 2011 Microchip Technology Inc. ...
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... DS70143E-page 121 © 2011 Microchip Technology Inc. ...
Page 122
... NOTES: DS70143E-page 122 © 2011 Microchip Technology Inc. ...
Page 123
... DATA CONVERTER INTERFACE (DCI) MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” ...
Page 124
... FIGURE 18-1: DCI MODULE BLOCK DIAGRAM F OSC Word Size Selection bits Frame Length Selection bits DCI Mode Selection bits Receive Buffer Registers w/Shadow Transmit Buffer Registers w/Shadow DS70143E-page 124 BCG Control bits Sample Rate /4 Generator Frame Synchronization Generator DCI Buffer ...
Page 125
... DCI Module Operation 18.3.1 MODULE ENABLE The DCI module is enabled or disabled by setting/ clearing the DCIEN control bit in the DCICON1 SFR. Clearing the DCIEN control bit has the effect of reset- ting the module. In particular, all counters associated with CSCK generation, frame sync, and the DCI buffer control unit are reset ...
Page 126
... In the I S mode, a frame sync signal having a 50% duty cycle is generated. The period of the I signal in CSCK cycles is determined by the word size and frame sync generator control bits. A new I transfer boundary is marked by a high-to-low or a low-to-high transition edge on the COFS pin. ...
Page 127
... BIT CLOCK GENERATOR The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate (period) is set by writing a non-zero 12-bit value to the BCG<11:0> control bits in the DCICON3 SFR. When the BCG<11:0> bits are set to zero, the bit clock will be disabled. If the BCG< ...
Page 128
... SAMPLE CLOCK EDGE CONTROL BIT The sample clock edge (CSCKE) control bit determines the sampling edge for the CSCK signal. If the CSCK bit is cleared (default), data will be sampled on the falling edge of the CSCK signal. The AC-Link protocols and most Multi-Channel formats require that data be sam- pled on the falling edge of the CSCK signal ...
Page 129
... BUFFER LENGTH CONTROL The amount of data that is buffered between interrupts is determined by the buffer length (BLEN<1:0>) control bits in the DCICON1 SFR. The size of the transmit and receive buffers may be varied from data words using the BLEN control bits. The BLEN control bits are compared to the current value of the DCI buffer control unit address counter ...
Page 130
... SLOT STATUS BITS The SLOT<3:0> status bits in the DCISTAT SFR indi- cate the current active time slot. These bits will corre- spond to the value of the frame sync generator counter. The user may poll these status bits in software when a DCI interrupt occurs to determine what time slot data was last received and which time slot data should be loaded into the TXBUF registers ...
Page 131
... The 20-bit mode treats each 256-bit AC-Link frame as sixteen, 16-bit time slots. In the 20-bit AC-Link mode, the module operates as if COFSG<3:0> = 1111 and WS<3:0> = 1111. The data alignment for 20-bit data slots is ignored. For example, an entire AC-Link data frame can be transmitted and received in a packed fashion by setting all bits in the TSCON and RSCON SFRs ...
Page 132
... DS70143E-page 132 © 2011 Microchip Technology Inc. ...
Page 133
... ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” ...
Page 134
... ADC Result Buffer The module contains a 16-word dual port read only buf- fer, called ADCBUF0...ADCBUFF, to buffer the ADC results. The RAM is 12 bits wide but the data obtained is represented in one of four different 16-bit data for- mats. The contents of the sixteen ADC Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...
Page 135
... Programming the Start of Conversion Trigger The conversion trigger will terminate acquisition and start the requested conversions. The SSRC<2:0> bits select the source of the conversion trigger. The SSRC bits provide for up to four alternate sources of conversion trigger. When SSRC<2:0> = 000, the conversion trigger is under software control ...
Page 136
... ADC Speeds The dsPIC30F 12-bit ADC specifications permit a max- imum of 200 ksps sampling rate. The table below sum- marizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. TABLE 19-1: 12-BIT ADC EXTENDED CONVERSION RATES ...
Page 137
... The following figure depicts the recommended circuit for the conversion rates above 100 ksps. The dsPIC30F6014A is shown as an example. FIGURE 19-2: ADC VOLTAGE REFERENCE SCHEMATIC 0.1 μF 0.01 μF 10 The configuration procedures below give the required setup values for the conversion speeds above 100 ksps ...
Page 138
... FIGURE 19-3: CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START SAMPLING TIME T SAMP = ADCLK SAMP DONE ADCBUF0 ADCBUF1 Instruction Execution BSET ADCON1, ASAM 19.8 ADC Acquisition Requirements The analog input model of the 12-bit ADC is shown in Figure 19-4. The total sampling time for the ADC is a function of the internal amplifier settling time and the holding capacitor charge time ...
Page 139
... Module Power-down Modes The module has 2 internal Power modes. When the ADON bit is ‘1’, the module is in Active mode fully powered and functional. When ADON is ‘0’, the module is in Off mode. The dig- ital and analog portions of the circuit are disabled for maximum current savings ...
Page 140
... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the ADC port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (out- ...
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... Microchip Technology Inc. DS70143E-page 141 ...
Page 142
... NOTES: DS70143E-page 142 © 2011 Microchip Technology Inc. ...
Page 143
... SYSTEM INTEGRATION Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
Page 144
... TABLE 20-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 XT 4 MHz-10 MHz crystal on OSC1:OSC2 XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 145
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2011 Microchip Technology Inc. F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up ...
Page 146
... Oscillator Configurations 20.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<2:0> Configuration bits that select one of four oscillator groups, and b) FPR<4:0> Configuration bits that select the oscillator choices within the primary group. ...
Page 147
... OSCILLATOR START-UP TIMER (OST) In order to ensure that a crystal oscillator (or ceramic resonator) has started and stabilized, an Oscillator Start-up Timer is included simple 10-bit counter that counts 1024 T cycles before releasing the OSC oscillator clock to the rest of the system. The time-out period is designated as T ...
Page 148
... LOW-POWER RC OSCILLATOR (LPRC) The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of 512 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT) circuit, WDT and clock monitor circuits. It may also be used to provide a low ...
Page 149
... OSCCON and OSCTUN and one Configuration register, FOSC. Note: The description of the OSCCON and OSCTUN SFRs, as well as the FOSC Configuration register provided in this section are applicable dsPIC30F6011A/6012A/6013A/6014A devices in the dsPIC30F product family. © 2011 Microchip Technology Inc. only to the DS70143E-page 149 ...
Page 150
... REGISTER 20-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-y R-y — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 POST<1:0> LOCK bit 7 Legend Values dependent Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Group Selection bits (read-only) 111 = PLL Oscillator ...
Page 151
... REGISTER 20-2: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 -4 Unimplemented: Read as ‘0’ bit 3-0 TUN< ...
Page 152
... REGISTER 20-3: FOSC: OSCILLATOR CONFIGURATION REGISTER U-0 U-0 U-0 — — — bit 23 R/P R/P U-0 FCKSM<1:0> — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 23-16 Unimplemented: Read as ‘0’ ...
Page 153
... Reset The dsPIC30F differentiates between various kinds of Reset: • Power-on Reset (POR) • MCLR Reset during normal operation • MCLR Reset during Sleep • Watchdog Timer (WDT) Reset (during normal operation) • Programmable Brown-out Reset (BOR) • RESET Instruction • ...
Page 154
... FIGURE 20-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR OST Time-out PWRT Time-out Internal Reset FIGURE 20-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR OST Time-out PWRT Time-out Internal Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 155
... POR with Long Crystal Start-up Time (with FSCM Enabled) The oscillator start-up circuitry is not linked to the POR circuitry. Some crystal circuits (especially low frequency crystals) will have a relatively long start-up time. There- fore, one or more of the following conditions is possible after the POR timer and the PWRT have expired: • ...
Page 156
... Table 20-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table implies that all the bits are negated prior to the action specified in the condition column. TABLE 20-5: ...
Page 157
... Watchdog Timer (WDT) 20.5.1 WATCHDOG TIMER OPERATION The primary function of the Watchdog Timer (WDT reset the processor in the event of a software malfunction. The WDT is a free running timer, which runs off an on-chip RC oscillator, requiring no external component. Therefore, the WDT timer will continue to operate even if the main processor clock (e ...
Page 158
... Any interrupt that is individually enabled (using the corresponding IE bit) and meets the prevailing priority level will be able to wake-up the processor. The proces- sor will process the interrupt and branch to the ISR. The Sleep status bit in RCON register is set upon wake-up. ...
Page 159
... Peripheral Module Disable (PMD) Registers The Peripheral Module Disable (PMD) registers pro- vide a method to disable a peripheral module by stop- ping all clock sources supplied to that module. When a peripheral is disabled via the appropriate PMD control bit, the peripheral minimum power consumption state ...
Page 160
... DS70143E-page 160 © 2011 Microchip Technology Inc. ...
Page 161
... INSTRUCTION SET SUMMARY Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
Page 162
... All instructions are a single word, except for certain double word instructions, which were made double word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. ...
Page 163
... TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Wb Base W register ∈ {W0..W15} Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd Destination W register ∈ Wdo { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ ...
Page 164
... TABLE 21-2: INSTRUCTION SET OVERVIEW Base Assembly Assembly Syntax Instr # Mnemonic 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 165
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Assembly Syntax Instr # Mnemonic 9 BTG BTG f,#bit4 BTG Ws,#bit4 10 BTSC BTSC f,#bit4 BTSC Ws,#bit4 11 BTSS BTSS f,#bit4 BTSS Ws,#bit4 12 BTST BTST f,#bit4 BTST.C Ws,#bit4 BTST.Z Ws,#bit4 BTST.C Ws,Wb BTST.Z Ws,Wb 13 BTSTS BTSTS f,#bit4 BTSTS ...
Page 166
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Assembly Syntax Instr # Mnemonic 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R FF1R ...
Page 167
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Assembly Syntax Instr # Mnemonic 48 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd 49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd , AWB 51 MUL MUL.SS Wb,Ws,Wnd MUL.SU Wb,Ws,Wnd MUL.US Wb,Ws,Wnd MUL.UU Wb,Ws,Wnd MUL.SU Wb,#lit5,Wnd MUL.UU Wb,#lit5,Wnd MUL f 52 NEG ...
Page 168
... TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Assembly Syntax Instr # Mnemonic 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 67 SAC SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo Ws,Wnd 69 SETM SETM f SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd ...
Page 169
... DEVELOPMENT SUPPORT ® The PIC microcontrollers and dsPIC controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment ® - MPLAB IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families ...
Page 170
... MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...
Page 171
... MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulat- ® ing the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller ...
Page 172
... PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchip’s Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...
Page 173
... ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual” (DS70046). Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability ...
Page 174
... DC Characteristics TABLE 23-1: OPERATING MIPS VS. VOLTAGE V Range Temp Range DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C TABLE 23-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F601xA-30I Operating Junction Temperature Range ...
Page 175
... TABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. (2) Operating Voltage DC10 V Supply Voltage DD DC11 V Supply Voltage DD DC12 V RAM Data Retention Voltage DR DC16 V V Start Voltage POR DD to ensure internal Power-on Reset signal DC17 S V Rise Rate VDD ...
Page 176
... TABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC31a 3.1 6 DC31b 3.2 6 DC31c 3.1 6 DC31e 5.7 9 DC31f 5.5 9 DC31g 5.5 9 DC30a 10 15 DC30b 10 15 DC30c 10 15 DC30e 17 26 DC30f 17 26 DC30g 17 26 DC23a 19 30 DC23b ...
Page 177
... TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current (I ) IDLE DC51a 2.5 5 DC51b 2.6 5 DC51c 2.6 5 DC51e 5.5 8 DC51f 5.3 8 DC51g 5.2 8 DC50a 6.7 13 DC50b 6.7 13 DC50c 6.8 13 DC50e 8.5 19 DC50f 8.5 19 DC50g 8.6 19 DC43a 8.7 ...
Page 178
... TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter Typical Max No. Power Down Current ( DC60a 0.5 — DC60b 1 40 DC60c 24 65 DC60e 0.7 — DC60f 4 55 DC60g 35 90 DC61a 9 20 DC61b 9 20 DC61c 8 20 DC61e 18 40 DC61f 16 40 DC61g 15 40 DC62a ...
Page 179
... TABLE 23-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Input Low Voltage IL DI10 I/O pins: with Schmitt Trigger buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL V Input High Voltage ...
Page 180
... TABLE 23-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Output Low Voltage OL DO10 I/O ports DO16 OSC2/CLKOUT ( Osc mode) V Output High Voltage OH DO20 I/O ports DO26 OSC2/CLKOUT ( Osc mode) Capacitive Loading Specs (2) on Output Pins DO50 C 2 OSC2/SOSC2 pin ...
Page 181
... TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL DC CHARACTERISTICS Param Symbol Characteristic No. LV10 V LVDL Voltage on V PLVD high to low LV15 V External LVD input pin LVDIN threshold voltage Note 1: These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 23-2: ...
Page 182
... TABLE 23-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param Symbol Characteristic No. (2) BO10 V BOR Voltage BOR V transition high to DD low BO15 V BHYS Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. ...
Page 183
... AC Characteristics and Timing Parameters The information contained in this section defines dsPIC30F AC characteristics and timing parameters. TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) AC CHARACTERISTICS Operating temperature Operating voltage V FIGURE 23-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – ...
Page 184
... TABLE 23-14: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OS10 F External CLKIN Frequency OSC (External clocks allowed only in EC mode) Oscillator Frequency OS20 1/F OSC OSC OSC OS25 T Instruction Cycle Time CY (2) OS30 TosL, External Clock in (OSC1) TosH High or Low Time ...
Page 185
... TABLE 23-15: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Input Frequency Range PLLI OS51 F On-Chip PLL Output SYS OS52 T PLL Start-up Time (Lock Time) LOC Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested ...
Page 186
... TABLE 23-17: INTERNAL CLOCK TIMING EXAMPLES Clock F OSC Oscillator T CY (1) (MHz) Mode EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F TABLE 23-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 187
... FIGURE 23-5: CLKOUT AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 23-3 for load conditions. TABLE 23-20: CLKOUT AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 T R Port output rise time IO DO32 ...
Page 188
... FIGURE 23-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 23-3 for load conditions. ...
Page 189
... TABLE 23-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY10 TmcL MCLR Pulse Width (low) SY11 T Power-up Timer Period PWRT SY12 T Power-on Reset Delay POR SY13 T I/O high-impedance from MCLR ...
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... FIGURE 23-7: BAND GAP START-UP TIME CHARACTERISTICS 0V Enable Band Gap (see Note) Note: Set LVDEN bit (RCON<12>) or BOREN bit (FBORPOR<7>). TABLE 23-22: BAND GAP START-UP TIME REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY40 T Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. ...
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... FIGURE 23-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRX Note: Refer to Figure 23-3 for load conditions. TABLE 23-23: TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TA10 T H TxCK High Time TX TA11 T L TxCK Low Time ...
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... TABLE 23-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TtxH TB10 TxCK High Time TB11 TtxL TxCK Low Time TB15 TtxP TxCK Input Period Synchronous, TB20 T - Delay from External TxCK Clock CKEXT Edge to Timer Increment MRL Note 1: Timer2 and Timer4 are Type B ...
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... FIGURE 23-9: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS IC X Note: Refer to Figure 23-3 TABLE 23-26: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. IC10 TccL ICx Input Low Time IC11 TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing ...
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... FIGURE 23-11: OC/PWM MODULE TIMING CHARACTERISTICS OCFA/OCFB OC15 OCx TABLE 23-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Para Symb m Characteristic ol No. OC15 T Fault Input to PWM I/O FD Change OC20 T Fault Input Pulse Width FLT Note 1: These parameters are characterized but not tested in manufacturing. ...
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... FIGURE 23-12: DCI MODULE (MULTICHANNEL, I CSCK (SCKE = 0) CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 23-3 for load conditions. © 2011 Microchip Technology Inc MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN ...
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... TABLE 23-29: DCI MODULE (MULTICHANNEL CHARACTERISTICS Param Symbol Characteristic No. CS10 Tc CSCK Input Low Time SCKL (CSCK pin is an input) CSCK Output Low Time (CSCK pin is an output) CS11 Tc CSCK Input High Time SCKH (CSCK pin is an input) CSCK Output High Time ...
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... FIGURE 23-13: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 SYNC (COFS) CS80 MSb LSb SDO (CSDO) MSb IN SDI (CSDI) CS65 CS66 TABLE 23-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. CS60 T BIT_CLK Low Time ...
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... FIGURE 23-14: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SDOx SP31 SDIx MSb IN SP40 SP41 Note: Refer to Figure 23-3 for load conditions. TABLE 23-31: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
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... FIGURE 23-15: SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS SP36 SCK X (CKP = 0) SP11 SCK X (CKP = 1) SDO MSb X SP40 SP30,SP31 SDI MSb IN X SP41 TABLE 23-32: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SP10 TscL SCK output low time ...
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... FIGURE 23-16: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) SP35 SDO X SDI SDI X SP40 TABLE 23-33: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SP70 TscL SCK Input Low Time ...