ATMEGA2561V-8MI Atmel, ATMEGA2561V-8MI Datasheet - Page 30
![IC AVR MCU 256K 8MHZ 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA2561V-8MI
Manufacturer Part Number
ATMEGA2561V-8MI
Description
IC AVR MCU 256K 8MHZ 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA2561V-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA2561V-8MI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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8.1.3
8.1.4
2549M–AVR–09/10
Pull-up and Bus-keeper
Timing
Figure 8-2.
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in
on page
these lines are tri-stated by the XMEM interface.
External Memory devices have different timing requirements. To meet these requirements, the
XMEM interface provides four different wait-states as shown in
tant to consider the timing specification of the External Memory device before selecting the wait-
state. The most important parameters are the access time for the external memory compared to
the set-up requirement. The access time for the External Memory is defined to be the time from
receiving the chip select/address until the data of this address actually is driven on the bus. The
access time cannot exceed the time from the ALE pulse must be asserted low until data is stable
during a read sequence (See t
378 - 381). The different wait-states are set up in software. As an additional feature, it is possible
to divide the external memory space in two sectors with individual wait-state settings. This
makes it possible to connect two different memory devices with different timing requirements to
the same XMEM interface. For XMEM interface timing details, please refer to
page 378
in the
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
“External Data Memory Timing” on page
38. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while
to
Table 30-16 on page 381
External SRAM Connected to the AVR
AVR
AD7:0
A15:8
ALE
WR
RD
LLRL
ATmega640/1280/1281/2560/2561
+ t
RLRH
and
- t
Figure 30-9 on page 381
DVRH
D
G
“XMCRB – External Memory Control Register B”
378.
in Tables 30-9 through Tables 30-16 on pages
Q
Table 8-3 on page
D[7:0]
A[15:8]
A[7:0]
RD
WR
SRAM
to
Figure 30-12 on page 383
Table 30-9 on
38. It is impor-
30
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