DSPIC30F4013T-20I/ML Microchip Technology, DSPIC30F4013T-20I/ML Datasheet - Page 112

• Manufacturer Part Number: DSPIC30F4013T-20I/ML
• Description: IC DSPIC MCU/DSP 48K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013T-20I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4013T20IM

dsPIC30F3014/4013
17.5.6
Transmit interrupts can be divided into 2 major groups,
each including various conditions that generate
interrupts:
• Transmit Interrupt:
• Transmit Error Interrupts:
FIGURE 17-2:
DS70138C-page 110
T
- Transmitter Warning Interrupt:
- Transmitter Error Passive:
- Bus Off:
At least one of the three transmit buffers is empty
(not scheduled) and can be loaded to schedule a
message for transmission. Reading the TXnIF
flags will indicate which transmit buffer is available
and caused the interrupt.
A transmission error interrupt will be indicated by
the ERRIF flag. This flag shows that an error con-
dition occurred. The source of the error can be
determined by checking the error flags in the CAN
Interrupt Status register, CiINTF. The flags in this
register are related to receive and transmit errors.
Input Signal
Q
The TXWAR bit indicates that the transmit error
counter has reached the CPU warning limit of
96.
The TXEP bit (CiINTF<12>) indicates that the
transmit error counter has exceeded the error
passive limit of 127 and the module has gone to
error passive state.
The TXBO bit (CiINTF<13>) indicates that the
transmit error counter has exceeded 255 and
the module has gone to the bus off state.
TRANSMIT INTERRUPTS
Sync
CAN BIT TIMING
Segment
Prop
Advance Information
Segment 1
Phase
Sample Point
17.6
All nodes on any particular CAN bus must have the
same nominal bit rate. In order to set the baud rate, the
following parameters have to be initialized:
• Synchronization Jump Width
• Baud Rate Prescaler
• Phase Segments
• Length determination of Phase Segment 2
• Sample Point
• Propagation Segment bits
17.6.1
All controllers on the CAN bus must have the same
baud rate and bit length. However, different controllers
are not required to have the same master oscillator
clock. At different clock frequencies of the individual
controllers, the baud rate has to be adjusted by
adjusting the number of time quanta in each segment.
The nominal bit time can be thought of as being divided
into separate non-overlapping time segments. These
segments are shown in Figure 17-2.
• Synchronization Segment (Sync Seg)
• Propagation Time Segment (Prop Seg)
• Phase Segment 1 (Phase1 Seg)
• Phase Segment 2 (Phase2 Seg)
The time segments and also the nominal bit time are
made up of integer units of time called time quanta or
T
of 8 T
the minimum nominal bit time is 1 µsec corresponding
to a maximum bit rate of 1 MHz.
Q
. By definition, the nominal bit time has a minimum
Q
and a maximum of 25 T
Baud Rate Setting
BIT TIMING
Segment 2
Phase
 2004 Microchip Technology Inc.
Q
. Also, by definition,
Sync