ATMEGA16-16AUR Atmel, ATMEGA16-16AUR Datasheet - Page 157
![MCU AVR 128KB FLASH 16MHZ 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA16-16AUR
Manufacturer Part Number
ATMEGA16-16AUR
Description
MCU AVR 128KB FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16L-8MI.pdf
(357 pages)
Specifications of ATMEGA16-16AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16-16AUR
Manufacturer:
Encoders
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Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
Flushing the Receive
Buffer
Asynchronous
Data Reception
Asynchronous Clock
Recovery
2466T–AVR–07/10
receptions will therefore be lost. When disabled (that is, the RXEN is set to zero) the Receiver
will no longer override the normal function of the RxD port pin. The receiver buffer FIFO will be
flushed when the receiver is disabled. Remaining data in the buffer will be lost
The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is
cleared. The following code example shows how to flush the receive buffer.
Note:
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the receiver.
The asynchronous reception operational range depends on the accuracy of the internal baud
rate clock, the rate of the incoming frames, and the frame size in number of bits.
The clock recovery logic synchronizes internal clock to the incoming serial frames.
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and 8 times the baud rate for Double Speed mode. The horizon-
tal arrows illustrate the synchronization variation due to the sampling process. Note the larger
time variation when using the double speed mode (U2X = 1) of operation. Samples denoted zero
are samples done when the RxD line is idle (that is, no communication activity).
Figure 73. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the
start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in
the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-
ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the
Assembly Code Example
C Code Example
(U2X = 0)
(U2X = 1)
Sample
Sample
USART_Flush:
void USART_Flush( void )
{
}
RxD
sbis UCSRA, RXC
ret
in
rjmp USART_Flush
unsigned char dummy;
while ( UCSRA & (1<<RXC) ) dummy = UDR;
1. See “About Code Examples” on page 7.
r16, UDR
0
0
IDLE
(1)
0
1
1
2
(1)
3
2
4
5
3
6
7
4
8
START
9
5
10
11
6
12
13
7
14
ATmega16(L)
15
8
16
1
1
2
BIT 0
Figure 73
3
2
157
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