LPC2210FBD144,551 NXP Semiconductors, LPC2210FBD144,551 Datasheet - Page 15

• Manufacturer Part Number: LPC2210FBD144,551
• Description: IC ARM7 MCU 16KRAM W/ADC 144LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2200r

Specifications of LPC2210FBD144,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: OM10091 - KIT DEV PHYCORE-ARM7/LPC2220568-1757 - BOARD EVAL FOR LPC220X ARM MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 568-1227; 935275683551; LPC2210FBD144-S

NXP Semiconductors
6. Functional description
LPC2210_2220_6
Product data sheet
6.1 Architectural overview
6.2 On-chip SRAM
6.3 Memory map
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on RISC
principles, and the instruction set and related decode mechanism are much simpler than
those of microprogrammed CISC. This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed
as 8-bit, 16-bit, and 32-bit. The LPC2210 and LPC2210/01 provide 16 kB of static RAM,
and the LPC2220 provides 64 kB of static RAM.
The LPC2210/2220 memory maps incorporate several distinct regions, as shown in
Figure
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either
on-chip bootloader, external memory BANK0 or on-chip static RAM. This is described in
Section 6.20 “System
•
•
The standard 32-bit ARM set.
A 16-bit Thumb set.
4.
Rev. 06 — 11 December 2008
control”.
16/32-bit ARM microcontrollers
LPC2210/2220
© NXP B.V. 2008. All rights reserved.
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