LPC2210FBD144,551 NXP Semiconductors, LPC2210FBD144,551 Datasheet - Page 39

• Manufacturer Part Number: LPC2210FBD144,551
• Description: IC ARM7 MCU 16KRAM W/ADC 144LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2200r

Specifications of LPC2210FBD144,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: OM10091 - KIT DEV PHYCORE-ARM7/LPC2220568-1757 - BOARD EVAL FOR LPC220X ARM MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 568-1227; 935275683551; LPC2210FBD144-S

NXP Semiconductors
Table 14.
C
[1]
[2]
[3]
[4]
[5]
[6]
Table 15.
LPC2210_2220_6
Product data sheet
Symbol
t
t
t
t
t
t
t
Access cycle
standard read
standard write
burst read - initial
burst read - subsequent 3
BLSHDNV
CHDV
CHWEL
CHBLSL
CHWEH
CHBLSH
CHDNV
L
= 25 pF; T
Except on initial access, in which case the address is set up T
T
Latest of address valid, CS LOW, OE LOW to data valid.
See the LPC2210/20 user manual UM10114_1 for a description of the WSTn bits.
Address valid to data valid.
Earliest of CS HIGH, OE HIGH, address change to data invalid.
cy(CCLK)
External memory interface dynamic characteristics
Standard read access specifications
Parameter
BLS HIGH to data invalid
time
XCLK HIGH to data valid
time
XCLK HIGH to WE LOW time
XCLK HIGH to BLS LOW
time
XCLK HIGH to WE HIGH
time
XCLK HIGH to BLS HIGH
time
XCLK HIGH to data invalid
time
=
amb
1
CCLK
= 40 C.
.
Max frequency
f
f
f
f
MAX
MAX
MAX
MAX
--------------------------------
t
--------------------------------- -
t
------------------------------- -
t
-------------------------------- -
t
RAM
WRITE
INIT
ROM
2
2
1
Conditions
+
+
+
WST 1
WST 1
+
+
WST 2
+
1
20 ns
20 ns
+
20 ns
Rev. 06 — 11 December 2008
5 ns
WST 1
WST setting
WST
integer
N/A
WST 1
WST 2
cy(CCLK)
[2]
0; round up to
Min
(2
-
-
-
-
-
-
t
------------------------------- - 2
t
-------------------------------- 2
t
------------------------------------------- -
INIT
RAM
WRITE
t
t
cy CCLK
earlier.
cy CCLK
…continued
T
t
cy CCLK
+
cy(CCLK)
+
20 ns
20 ns
–
t
CYC
–
)
–
+
5
5
Memory access time requirement
t
t
t
t
INIT
RAM
WRITE
ROM
16/32-bit ARM microcontrollers
LPC2210/2220
t
t
t
cy CCLK
cy CCLK
cy CCLK
Typ Max
-
-
-
-
-
-
-
t
cy CCLK
(2
10
10
10
10
10
10
–
T
20 ns
© NXP B.V. 2008. All rights reserved.
2
2
cy(CCLK)
+
+
1
WST 1
WST 1
+
WST 2
) + 5 ns
–
–
20 ns
39 of 50
20 ns
–
Unit
ns
ns
ns
ns
ns
ns
5 ns