SX28AC/SS Parallax Inc, SX28AC/SS Datasheet - Page 13

• Manufacturer Part Number: SX28AC/SS
• Description: IC MCU 2K FLASH 50MHZ 28SSOP
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX28AC/SS

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 75MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 136 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Product: Microcontroller Basic Stamps
• Flash: 2 KBytes
• Timers: 8 bit
• Operating Supply Voltage: 3 to 5.5 V
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Parallax SX20AC/SX28AC
4.0
The CPU uses a set of special-function registers to control
the operation of the device.
The CPU registers include an 8-bit working register (W),
which serves as a pseudo accumulator. It holds the second
operand of an instruction, receives the literal in immediate
type instructions, and also can be program selected as the
destination register.
A set of 31 file registers serves as the primary
accumulator. One of these registers holds the first operand
of an instruction and another can be program-selected as
the destination register. The first eight file registers
include the Real-Time Clock/Counter register (RTCC),
the lower eight bits of the 11-bit Program Counter (PC),
the 8-bit STATUS register, three port control registers for
Port A, Port B, Port C, the 8-bit File Select Register
(FSR), and INDF used for indirect addressing.
The five low-order bits of the FSR register select one of
the 31 file registers in the indirect addressing mode.
Calling for the file register located at address 00h (INDF)
in any of the file-oriented instructions selects indirect
addressing, which uses the FSR register. It should be
noted that the file register at address 00h is not a
physically implemented register. The CPU also contains
an 8 level, 11-bit hardware push/pop stack for subroutine
linkage.
*In the SX20 package, Port C is not used, and address 07h is
available as a general-purpose RAM location.
4.1.
The PC register holds the lower eight bits of the program
counter. It is accessible at run time to perform branch
operations.
4.2.
The STATUS register holds the arithmetic status of the
ALU, the page select bits, and the reset state. The
STATUS register is accessible during run time, except
that bits PD and TO are read-only. It is recommended that
only SETB and CLRB instructions be used on this
© Parallax Inc.
Address
00h
01h
02h
03h
04h
05h
06h
07h
SPECIAL-FUNCTION REGISTERS
PC Register (02h)
STATUS Register (03h)
Table 4-1:
INDF
RTCC
PC
STATUS
FSR
RA
RB
RC*
Name
Special-Function Register
Used for indirect addressing
Real Time Clock/Counter
Program Counter (low byte)
Holds status bits of ALU
File Select Register
Port RA control register
Port RB control register
Port RC control register
Function
Page 13 of 51
register. Care should be exercised when writing to the
STATUS register as the ALU status bits are updated upon
completion of the write operation, possibly leaving the
STATUS register with a result that is different than
intended.
Bit 7-5: Page select bits PA2:PA0
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Bit 7
PA2
000 = Page 0 (000h - 01FFh)
001 = Page 1 (200h - 03FFh)
010 = Page 2 (400h - 05FFh)
011 = Page 3 (600h - 07FFh)
Time Out bit, TO
1 = Set to 1 after power up and upon execution
of CLRWDT or SLEEP instructions
0 = A watchdog time-out occurred
Power Down bit, PD
1= Set to a 1 after power up and upon execution
of the CLRWDT instruction
0 = Cleared to a ‘0’ upon execution of SLEEP
instruction
Zero bit, Z
1 = Result of math operation is zero
0 = Result of math operation is non-zero
Digit Carry bit, DC
After Addition:
1 = A carry from bit 3 occurred
0 = No carry from bit 3 occurred
After Subtraction:
1 = No borrow from bit 3 occurred
0 = A borrow from bit 3 occurred
Carry bit, C
After Addition:
1 = A carry from bit 7 of the result occurred
0 = No carry from bit 7 of the result occurred
After Subtraction:
1 = No borrow from bit 7 of the result occurred
0 = A borrow from bit 7 of the result occurred
Rotate (RR or RL) Instructions:
The carry bit is loaded with the low or high order
bit, respectively. When CF bit is cleared, Carry
bit works as input For ADD and SUB
instructions.
PA1
PA0
TO
PD
Z
Rev 1.6 11/20/2006
www.parallax.com
DC
Bit 0
C