SX28AC/SS Parallax Inc, SX28AC/SS Datasheet - Page 21

• Manufacturer Part Number: SX28AC/SS
• Description: IC MCU 2K FLASH 50MHZ 28SSOP
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX28AC/SS

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 75MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 136 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Product: Microcontroller Basic Stamps
• Flash: 2 KBytes
• Timers: 8 bit
• Operating Supply Voltage: 3 to 5.5 V
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Parallax SX20AC/SX28AC
8.0
The device supports both internal and external maskable
interrupts. The internal interrupt is generated as a result of
the RTCC rolling over from 0FFh to 00h. This interrupt
source has an associated enable bit located in the
OPTION register. There is no pending bit associated with
this interrupt.
Port B provides the source for eight external software
selectable, edge sensitive interrupts. These interrupt
sources share logic with the Multi-Input Wakeup
circuitry. The WKEN_B register allows interrupt from
Port B to be individually enabled or disabled. Clearing a
bit in the WKEN_B register enables the interrupt on the
corresponding Port B pin. The WKED_B selects the
© Parallax Inc.
INTERRUPT SUPPORT
Figure 8-1: Interrupt Structure
Page 21 of 51
transition edge to be either positive or negative. The
WKEN_B and WKED_B registers are set to FFh upon
reset. Setting a bit in the WKED_B register selects the
falling edge while clearing the bit selects the rising edge
on the corresponding Port B pin.
The WKPND_B register serves as the external interrupt
pending register.
The WKPND_B register comes up a with random value
upon reset. The user program must clear the WKPND_B
register prior to enabling the interrupt. The proper
sequence is described in Section 7.2
Figure 8-1 shows the structure of the interrupt logic.
Rev 1.6 11/20/2006
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