Z8F0812SJ020EC Zilog, Z8F0812SJ020EC Datasheet - Page 117

• Manufacturer Part Number: Z8F0812SJ020EC
• Description: IC ENCORE MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0812SJ020EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-3228

Table 57. UART Control 1 Register (U0CTL1)
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
MPMD[1]
7
PSEL—Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
SBRK—Send Break
This bit pauses or breaks data transmission by forcing the Transmit data output to 0.
Sending a break interrupts any transmission in progress, so ensure that the transmitter has
finished sending data before setting this bit. The UART does not automatically generate a
STOP Bit when SBRK is deasserted. Software must time the duration of the Break and the
duration of any STOP Bit time desired following the Break.
0 = No break is sent.
1 = The output of the transmitter is zero.
STOP—STOP Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
MPMD[1:0]—Multiprocessor Mode
If Multiprocessor (9-bit) mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches
11 = The UART generates an interrupt request on all received data bytes for which
MPEN—Multiprocessor (9-bit) Enable
This bit is used to enable Multiprocessor (9-bit) mode.
0 = Disable Multiprocessor (9-bit) mode.
1 = Enable Multiprocessor (9-bit) mode.
the value stored in the Address Compare Register and on all successive data
bytes until an address mismatch occurs.
the most recent address byte matched the value in the Address Compare Register.
MPEN
6
MPMD[0]
5
MPBT
4
F43H
R/W
0
DEPOL
3
Universal Asynchronous Receiver/Transmitter
BRGCTL
Z8 Encore! XP
2
Product Specification
RDAIRQ
1
®
F0822 Series
IREN
0
104