Z8F0812SJ020EC Zilog, Z8F0812SJ020EC Datasheet - Page 132

• Manufacturer Part Number: Z8F0812SJ020EC
• Description: IC ENCORE MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0812SJ020EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-3228

PS022517-0508
Error Detection
SPI Interrupts
NUMBITS field in the SPIMODE Register must be set to be consistent with the other
SPI devices. The STR bit in the SPICTL Register can be used if desired to force a
“startup” interrupt. The BIRQ bit in the SPICTL Register and the SSV bit in the
SPIMODE Register is not used in SLAVE mode. The SPI Baud Rate Generator is not used
in SLAVE mode so the SPIBRH and SPIBRL Registers need not be initialized.
If the slave has data to send to the master, the data must be written to the SPIDAT
Register before the transaction starts (first edge of SCK when SS is asserted). If the
SPIDAT Register is not written prior to the slave transaction, the MISO pin outputs
whatever value is currently in the SPIDAT Register.
Due to the delay resulting from synchronization of the SPI input signals to the internal
system clock, the maximum SPICLK baud rate that can be supported in SLAVE mode is
the system clock frequency (XIN) divided by 8. This rate is controlled by the SPI Master.
The SPI contains error detection logic to support SPI communication protocols and recog-
nize when communication errors have occurred. The SPI Status Register indicates when a
data transmission error has been detected.
Overrun (Write Collision)
An overrun error (write collision) indicates a write to the SPI Data Register was attempted
while a data transfer is in progress (in either Master or Slave modes). An overrun sets the
OVR bit in the SPI Status Register to 1. Writing a 1 to OVR clears this error flag. The data
register is not altered when a write occurs while data transfer is in progress.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one Master is trying to communicate at the same
time (a multi-master collision). The mode fault is detected when the enabled Master’s SS
pin is asserted. A mode fault sets the COL bit in the SPI Status Register to 1. Writing a 1 to
COL clears this error Flag.
SLAVE Mode Abort
In SLAVE mode, if the SS pin deasserts before all bits in a character have been
transferred, the transaction aborts. When this condition occurs the
SPISTAT Register as well as the
time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previous
transaction left off. Writing a 1 to ABT clears this error flag.
When SPI interrupts are enabled, the SPI generates an interrupt after character transmis-
sion/reception completes in both Master and Slave modes. A character is defined to be 1
through 8 bits by the NUMBITS field in the SPI Mode Register. In SLAVE mode it is not
IRQ
bit (indicating the transaction is complete). The next
Z8 Encore! XP
Product Specification
ABT
Serial Peripheral Interface
bit is set in the
®
F0822 Series
119