LH7A404N0F000B2 Sharp Microelectronics, LH7A404N0F000B2 Datasheet - Page 12

• Manufacturer Part Number: LH7A404N0F000B2
• Description: IC ARM9 BLUESTREAK MCU 324CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-CABGA
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 425-2468; LH7A404N0F000B2

LH7A404
NOTES:
1. Signals beginning with ‘n’ are Active LOW.
2. The SCLK pin can source up to 12 mA and sink up to 20 mA.
3. Schmitt trigger input
4. Input only for JTAG boundary scan mode.
5. Output only for JTAG boundary scan mode.
6. These pins have alternate NAND Flash functions during boot-up
12
CABGA
W15
W18
U16
V15
T13
Y14
E12
A11
B11
B10
D6
A3
D5
C4
B3
A2
E5
D3
C2
B1
E3
See ‘DC Characteristics’.
when using the internal Boot ROM. Consult the Boot ROM
Chapter of the User’s Guide for more information.
Normal
MODE
JTAG
AN6
AN7
AN8
AN9
SCIO
SCCLK
nSCRESET
SCVCCEN
CTCLKIN
DREQ0
DACK0
DEOT0
DREQ1
DACK1
DEOT1
nTEST0
nTEST1
TDI
TCK
TDO
TMS
Table 2. nTEST Pin Function
SIGNAL
nTEST0
0
1
ADC channel 6
ADC channel 7
ADC channel 8
ADC channel 9
Smart Card Interface I/O
Smart Card Interface Clock
Smart Card Interface Reset
Smart Card Interface VCC Enable
Counter Timer Clock Input
DMA Request 0
DMA Acknowledge 0
DMA End of Transfer 0
DMA Request 1
DMA Acknowledge 1
DMA End of Transfer 1
Test Pin 0. Internal weak pull up to VDD. Status latched
at nPOR going HIGH. Pull LOW for JTAG mode. Pull
HIGH (or leave open) for Normal mode. See Table 2.
Test Pin 1. Internal weak pull up to VDD. Status latched
at nPOR going HIGH. Pull HIGH (or leave open) for both
JTAG and Normal mode. See Table 2.
JTAG Data In. Internal weak pull up to VDD.
JTAG Clock. Internal weak pull up to VDD.
JTAG Data Out
JTAG Test Mode Select. Internal weak pull up to VDD.
nTEST1
Table 1. LH7A404 Functional Pin List (Cont’d)
1
1
DESCRIPTION
nURESET
1
x
Version 1.0
Input with
Input with
RESET
STATE
pull-up
pull-up
High Z
LOW
LOW
LOW
Input
Input
Input
Input
LOW
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
STANDBY
Input with
Input with
STATE
pull-up
pull-up
Input
Input
Input
Input
LOW
LOW
LOW
32-Bit System-on-Chip
OUTPUT
DRIVE
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
4 mA
Data Sheet
I/O NOTES
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
3
5