LH7A404N0F000B2 Sharp Microelectronics, LH7A404N0F000B2 Datasheet - Page 25

• Manufacturer Part Number: LH7A404N0F000B2
• Description: IC ARM9 BLUESTREAK MCU 324CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-CABGA
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 425-2468; LH7A404N0F000B2

32-Bit System-on-Chip
• Two dedicated channels for M2M and external
• Ten fully independent, programmable DMA control-
• Channels assignable to one of a number of different
• Independent source and destination address regis-
• Two buffer descriptors per M2P and M2M channel to
• No AMBA wrapping bursts for DMA channels; only
• Buffer size independent of the peripheral’s packet
• Maskable interrupt generation
• Internal arbitration between DMA channels, plus
• DMA data transfer sizes, byte, word and quad-word
• Per-channel clock gating reducing power in chan-
the system processor for setting up DMA operations
and monitoring their status. System interrupts are gen-
erated when any/all of the DMA channels wish to
inform the processor to update the buffer descriptor.
The DMA controller can service 10 out of 20 possible
peripherals using the ten DMA channels, each with its
own peripheral DMA bus capable of simultaneously
transferring data in both directions.
Host peripherals can each use two DMA channels, one
for transmit and one for receive. The AC97 peripheral
can use six DMA channels (three transmit and three
receive) to allow different sample frequency data
queues to be handled with low software overhead.
Data Sheet
M2P/P2M
ler internal M2P/P2M channels (5 Tx and 5 Rx)
peripherals
ters. Source and destination can be programmed
to auto-increment or not auto-increment for M2M
channels
avoid potential data under/over-flow due to software
introduced latency. A buffer refers to the area in sys-
tem memory that is characterized by a buffer
descriptor, i.e., a start address and the length of the
buffer in bytes
incrementing bursts are supported
size for the internal M2P channels. Transfers can
automatically switch between buffers
support for an AHB bus arbiter
data transfers are supported using a 16-byte data.
Maximum data transfer size per M2M channel is
programmable
nels that have not been enabled by software. See
the ‘Clock and State Controller’ section.
The DMA Controller features:
A set of control and status registers are available to
The SD/MMC, UART[3:1], USB Device, and USB
Version 1.0
ture allowing block moves of data from one memory
address space to another with minimum of program
effort and time. An M2M software trigger capability is
provided. The DMA controller can also fill a block of
memory with data from a single location.
used in M2P/P2M mode. A set of external handshake
signals, DREQ, DACK and TC/DEOT are provided for
each of two M2M channels.
active, and active HIGH or LOW. The peripheral may
hold DREQ active for the duration of the block transfers
or may assert/deassert on each transfer.
LOW. DACK will assert and return to de-asserted with
each Read or Write, the timing coinciding with nOE or
nWE from the EBI.
ble direction and active polarity. When configured as an
Output, the DMA will assert Terminal Count (TC) on the
final transfer to coincide with the DACK, typically when
the byte count has expired. When configured as an
Input, the peripheral must assert DEOT concurrent with
DREQ for the final transfer in the block.
external peripheral or when the byte count expires,
whichever occurs first. Status bits indicate if the actual
byte count is equal to the programmed limit, and if the
count was terminated by peripheral asserting DEOT.
Terminating the transfer causes a DMA interrupt on that
channel and rollover to the ‘other’ buffer if so configured.
USB Device
• Compliant with USB 2.0 Full Speed specification
• Provides a high-level interface that removes the
• Compatible with both OpenHCI and Intel UHCI
• Supports full-speed (12 Mbit/s) functions
• Supports Suspend and Resume signalling.
USB Host Controller
• Open Host Controller Interface Specification (Open-
• Universal Serial Bus Specification 2.0 Full Speed
• Supports Low Speed and High Speed USB devices
• Root Hub has two Downstream Ports
• DMA functionality.
USB protocol details from firmware
standards
HCI) Rev. 1.0 Compliant
compatible
The DMA controller includes an M2M transfer fea-
The DMA controller’s M2M channels can also be
DREQ (input) can be programmed edge or level
DACK (output) can be programmed active HIGH or
TC/DEOT is a bidirectional signal with programma-
Transfer is terminated when DEOT is asserted by the
The features of the USB are:
The features of the USB Host Controller are:
LH7A404
25