LH7A404N0F000B2 Sharp Microelectronics, LH7A404N0F000B2 Datasheet - Page 43

• Manufacturer Part Number: LH7A404N0F000B2
• Description: IC ARM9 BLUESTREAK MCU 324CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F000B2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-CABGA
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: 425-2468; LH7A404N0F000B2

32-Bit System-on-Chip
SSP Waveforms
data frame formats:
• Texas Instruments SSI
• Motorola SPI
• National Semiconductor MICROWIRE
length, depending upon the programmed data size.
Each data frame is transmitted beginning with the
Most Significant Bit (MSB) i.e. ‘big endian’. For all
three formats, the SSP serial clock is held LOW (inac-
tive) while the SSP is idle. The SSP serial clock tran-
sitions only during active transmission of data. The
SSPFRM signal marks the beginning and end of a
Data Sheet
The Synchronous Serial Port (SSP) supports three
Each frame format is between 4 and 16 bits in
Figure 15. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer)
Figure 14. Texas Instruments Synchronous Serial Frame Format (Single Transfer)
SSPTXD/
SSPTXD/
SSPFRM
SSPRXD
SSPFRM
SSPRXD
SSPCLK
SSPCLK
tSSPCLK
tISSPIN
tOVSSPOUT
MSB
MSB
tOHSSPOUT
4 to 16 BITS
Version 1.0
4 to 16 BITS
frame. The SSPEN signal controls an off-chip line
driver’s output enable pin.
synchronous serial frame format, Figure 16 through
Figure 23 show the Motorola SPI format, and Figure 24
and Figure 25 show National Semiconductor’s MICRO-
WIRE data frame format.
is pulsed prior to each frame’s transmission for one
serial clock period beginning at its rising edge. For this
frame format, both the SSP and the external slave
device drive their output data on the rising edge of the
clock and latch data from the other device on the falling
edge. See Figure 14 and Figure 15.
Figure 14 and Figure 15 show Texas Instruments
For Texas Instruments SSI format, the SSPFRM pin
LSB
LSB
LH7A404-24
LH7A404-25
LH7A404
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