ZLF645E0H2864G Zilog, ZLF645E0H2864G Datasheet - Page 142

• Manufacturer Part Number: ZLF645E0H2864G
• Description: IC MCU 64K FLASH 1K RAM 28-SSOP
• Manufacturer: Zilog
• Series: Crimzon™ ZLFr

Specifications of ZLF645E0H2864G

• Core Processor: Z8 LXMC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.9 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Oscillator Type: -
• Other names: 269-4719

PS026407-0408
Voltage Brownout Standby
STOP Mode
HALT Mode
An on-chip voltage comparator circuit (VBO) checks that the V
for correct operation of the device in terms of Flash memory reads. A second on-chip
comparator circuit (subVBO) checks that the V
tion of the VBO circuit. If the V
be held in a reset state as long as V
and XTAL2 oscillator circuitry will be disabled thereby stopping the clock input to the
ZLF645 and saving power. If the V
point, the ZLF645 will remain in a reset state and the VBO comparator circuit will be
disabled for further power savings. When the power level returns to a value above the
VBO trip point, the device performs a power-on reset and functions normally.
STOP
ing the MCU supply current to a very low level. For STOP mode current specifications,
see
To enter STOP mode, first flush the instruction pipeline to avoid suspending execution in
mid-instruction. Execute a NOP instruction (OpCode =
appropriate sleep instruction, as given below:
STOP mode is terminated only by a reset, such as WDT time-out, POR, or one of the Stop
Mode Recovery events as described in
This condition causes the processor to restart the application program at address
Unlike a normal POR or WDT reset, a Stop Mode Recovery reset does not reset the
contents of some registers and bits. Register bits not reset by a Stop Mode Recovery are
highlighted in grey in the register tables. Register bit SMR[7] is set to 1 by a Stop Mode
Recovery.
HALT
The counter/timers, UART, and interrupts (IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5)
remain active. The devices are recovered by interrupts, either externally or internally
generated. An interrupt request must be executed (enabled) to exit HALT mode. After the
interrupt service routine, the program continues from the instruction after HALT mode.
Table 81
FF
6F
instruction turns OFF the internal clock and external crystal oscillation, thus reduc-
instruction turns off the internal CPU clock, but not the XTAL oscillation.
on page 160.
NOP
STOP
DD
DD
level drops below the VBO trip point, the ZLF645 will
; clear the pipeline
; enter STOP mode
DD
remains below this trip point value, and the XTAL1
Stop Mode Recovery Event Sources
level continues to drop below the subVBO trip
DD
level is high enough for proper opera-
ZLF645 Series Flash MCUs
FFh
) immediately before the
DD
Product Specification
Voltage Brownout Standby
is at the required level
on page 138.
000Ch
.
134