ZLF645E0H2864G Zilog, ZLF645E0H2864G Datasheet - Page 145

• Manufacturer Part Number: ZLF645E0H2864G
• Description: IC MCU 64K FLASH 1K RAM 28-SSOP
• Manufacturer: Zilog
• Series: Crimzon™ ZLFr

Specifications of ZLF645E0H2864G

• Core Processor: Z8 LXMC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.9 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Oscillator Type: -
• Other names: 269-4719

Table 69. Watchdog Timer Mode Register (WDTMR)
PS026407-0408
Bit
Field
Reset
R/W
Address
Bit Position
[7]
[3]
[2]
[6:4], [1:0]
Reset/Stop Mode Recovery Status
Note:
Note:
—
W
001_XX
010_XX
100_XX
7
0
000_00
000_01
000_10
000_11
WDTMR register cannot be read. The register is located in Bank F of the Expanded Reg-
ister Group at address location
This register is not reset after a Stop Mode Recovery.
Although not explicitly shown above, if any two bits of bits 6 through 4 are programmed to
1 or if all three bits are programmed to 0, then the time-out period depends on bits 1 and 0
only as shown for the [6:4]=000 case.
Read-only bit SMR[7]=0, if the previous reset was initiated by a Power-On Reset (includ-
ing Voltage Brownout or WDT resets). SMR[7]=1, if the previous reset was initiated by a
Stop Mode Recovery. A power-on, Voltage Brownout, or WDT reset restores all registers
Value
—
0
1
0
1
W
6
0
Time-Out Select
Description
Reserved —Reads are undefined; must write 0000.
WDT During STOP Mode —Determines if WDT is active during STOP mode.
Off.
WDT active during STOP mode.
WDT During HALT Mode —Determines if WDT is active during HALT mode.
See
Off.
WDT active during HALT mode.
Time-Out Select —Selects the WDT time period (see Note below).
5 ms minimum
10 ms minimum
20 ms minimum
80 ms minimum
320 ms minimum
1, 280 ms minimum
5,120 ms minimum
Figure 43 on page
W
5
0
W
4
0
WDT During STOP
Bank F: 0Fh; Linear: F0Fh
0Fh
133.
Mode
.
W
3
1
WDT During HALT
Mode
W
2
1
ZLF645 Series Flash MCUs
Reset/Stop Mode Recovery Status
Product Specification
Time-Out Select
W
1
0
W
0
1
137