MC68HC711E20CFN3 Freescale Semiconductor, MC68HC711E20CFN3 Datasheet - Page 110
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MC68HC711E20CFN3
Manufacturer Part Number
MC68HC711E20CFN3
Description
IC MCU 3MHZ 20K OTP 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC711E20CFN3
Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
20KB (20K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC711E20CFN3
Manufacturer:
FREESCALE
Quantity:
4 463
Company:
Part Number:
MC68HC711E20CFN3
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Resets and Interrupts
5.3.3 Computer Operating Properly (COP) Reset
Technical Data
110
CR[1:0]
0 0
0 1
1 0
1 1
E/2
Divide
E =
16
64
15
1
4
By
– 0 ms, + 32.8 ms
XTAL = 4.0 MHz
131.072 ms
32.768 ms
524.28 ms
Timeout
1.0 MHz
The MCU includes a COP system to help protect against software
failures. When the COP is enabled, the software is responsible for
keeping a free-running watchdog timer from timing out. When the
software is no longer being executed in the intended sequence, a
system reset is initiated.
The state of the NOCOP bit in the CONFIG register determines whether
the COP system is enabled or disabled. To change the enable status of
the COP system, change the contents of the CONFIG register and then
perform a system reset. In the special test and bootstrap operating
modes, the COP system is initially inhibited by the disable resets (DISR)
control bit in the TEST1 register. The DISR bit can subsequently be
written to 0 to enable COP resets.
The COP timer rate control bits CR[1:0] in the OPTION register
determine the COP timeout period. The system E clock is divided by 2
and then further scaled by a factor shown in
bits are 0, which selects the fastest timeout period. In normal operating
modes, these bits can be written only once within 64 bus cycles after
reset.
2.098 s
Table 5-1. COP Timer Rate Select
Resets and Interrupts
– 0 ms, + 16.4 ms
XTAL = 8.0 MHz
16.384 ms
65.536 ms
262.14 ms
Timeout
2.0 MHz
1.049 s
XTAL = 12.0 MHz
– 0 ms, + 10.9 ms
10.923 ms
43.691 ms
174.76 ms
699.05 ms
Timeout
3.0 MHz
Table
M68HC11E Family — Rev. 3.2
5-1. After reset, these
XTAL = 16.0 MHz
– 0 ms, + 8.2 ms
Timeout
4.0 MHz
8.19 ms
32.8 ms
131 ms
524 ms
MOTOROLA
15
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