MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 120

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5.10.3 Recommended BDM Connection
5.10.4 Deterministic Opcode Tracking
5-22
STATUS CONTROL BIT
S/C
16
Command and data transfers initiated by the development system should clear bit 16.
The current implementation ignores this bit; however, Freescale reserves the right to
use this bit for future enhancements.
In order to provide for use of development tools when an MCU is installed in a system,
Freescale recommends that appropriate signal lines be routed to a male Berg connec-
tor or double-row header installed on the circuit board with the MCU, as shown in the
following figure.
CPU32 function code outputs are augmented by two supplementary signals to monitor
the instruction pipeline. The instruction pipe (IPIPE) output indicates the start of each
new instruction and each mid-instruction pipeline advance. The instruction fetch (IF-
ETCH) output identifies the bus cycles in which the operand is loaded into the instruc-
tion pipeline. Pipeline flushes are also signaled with IFETCH. Monitoring these two
signals allows a bus analyzer to synchronize itself to the instruction stream and mon-
itor its activity.
15
Bit 16
0
0
1
1
1
Table 5-6 CPU Generated Message Encoding
Freescale Semiconductor, Inc.
Figure 5-11 BDM Connector Pinout
For More Information On This Product,
Figure 5-10 BDM Serial Data Word
CENTRAL PROCESSING UNIT
RESET
GND
GND
V
Go to: www.freescale.com
DD
DS
FFFF
FFFF
1
3
5
7
9
0000
0001
Data
xxxx
10
2
4
6
8
DATA FIELD
Valid Data Transfer
Command Complete; Status OK
Not Ready with Response; Come Again
BERR Terminated Bus Cycle; Data Invalid
Illegal Command
BERR
BKPT/DSCLK
FREEZE
IFETCH/DSI
IPIPE/DSO
32 BERG
Message Type
USER’S MANUAL
MC68332
0