MC68332ACFC25 Freescale Semiconductor, MC68332ACFC25 Datasheet - Page 75

• Manufacturer Part Number: MC68332ACFC25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332ACFC25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

SPCR2 — QSPI Control Register 2
SPIFIE — SPI Finished Interrupt Enable
WREN — Wrap Enable
WRTO — Wrap To
Bit 12 — Not Implemented
ENDQP — Ending Queue Pointer
Bits [7:4] — Not Implemented
NEWQP — New Queue Pointer Value
SPCR3 — QSPI Control Register 3
Bits [15:11] — Not Implemented
LOOPQ — QSPI Loop Mode
HMIE — HALTA and MODF Interrupt Enable
MC68332
MC68332TS/D
RESET:
RESET:
SPIFIE
15
15
0
0
0
SPCR2 contains QSPI configuration parameters. The CPU can read and write this register; the QSM
has read access only. Writes to SPCR2 are buffered. A write to SPCR2 that changes a bit value while
the QSPI is operating is ineffective on the current serial transfer, but becomes effective on the next se-
rial transfer. Reads of SPCR2 return the current value of the register, not of the buffer.
SPIFIE enables the QSPI to generate a CPU interrupt upon assertion of the status flag SPIF.
WREN enables or disables wraparound mode.
When wraparound mode is enabled, after the end of queue has been reached, WRTO determines
which address the QSPI executes.
This field contains the last QSPI queue address.
This field contains the first QSPI queue address.
SPCR3 contains QSPI configuration parameters. The CPU can read and write SPCR3, but the QSM
has read-only access.
LOOPQ controls feedback on the data serializer for testing.
HMIE controls CPU interrupts caused by the HALTA status flag or the MODF status flag in SPSR.
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
0 = Wraparound mode disabled
1 = Wraparound mode enabled
0 = Feedback path disabled
1 = Feedback path enabled
0 = HALTA and MODF interrupts disabled
1 = HALTA and MODF interrupts enabled
WREN
14
14
0
0
0
WRTO
13
13
0
0
0
12
12
0
0
0
0
Freescale Semiconductor, Inc.
11
11
For More Information On This Product,
0
0
0
LOOPQ
10
0
0
ENDQP
Go to: www.freescale.com
HMIE
0
9
0
HALT
8
0
8
0
7
0
0
7
6
0
0
5
0
0
4
0
0
SPSR
3
0
0
NEWQP
MOTOROLA
$YFFC1C
$YFFC1E
0
0
0
0
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