MC68HC705SR3CP Freescale Semiconductor, MC68HC705SR3CP Datasheet
MC68HC705SR3CP
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MC68HC05SR3 MC68HC705SR3 Technical Data M68HC05 Microcontrollers MC68HC05SR3D/H Rev. 2.1 08/2005 freescale.com ...
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GENERAL DESCRIPTION PIN DESCRIPTIONS INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS TIMER MC68HC705SR3 TPG ...
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GENERAL DESCRIPTION 2 PIN DESCRIPTIONS 3 INPUT/OUTPUT PORTS 4 MEMORY AND REGISTERS 5 RESETS AND INTERRUPTS 6 TIMER 7 ANALOG TO DIGITAL CONVERTER 8 CPU CORE AND INSTRUCTION SET 9 LOW POWER MODES 10 OPERATING MODES 11 ELECTRICAL SPECIFICATIONS ...
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High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Units All Trade Marks recognized. This document contains information on new products. Specifications and information herein are subject to change without notice. All products are sold on Freescale’s Terms & Conditions of Supply. ...
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Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; ...
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CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05SR3D/H) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, ...
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How could we improve this document? 9. How would you rate Motorola’s documentation? – In general – Against other semiconductor suppliers 10. Which semiconductor manufacturer provides the best technical documentation? 11. Which company (in any field) provides the best ...
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TABLE OF CONTENTS Paragraph Number 1.1 Features.................................................................................................................1-1 1.2 Mask Options.........................................................................................................1-2 2.1 Functional Pin Descriptions ...................................................................................2-1 2.2 OSC1 and OSC2 Connections ..............................................................................2-2 2.2.1 Crystal Oscillator..............................................................................................2-3 2.2.2 External Clock..................................................................................................2-3 2.2.3 RC Oscillator Option ........................................................................................2-4 2.3 Pin Assignments ....................................................................................................2-5 3.1 Parallel Ports .........................................................................................................3-1 ...
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Paragraph Number 4.1 I/O Registers ......................................................................................................... 4-1 4.2 RAM ......................................................................................................................4-1 4.3 ROM ......................................................................................................................4-1 4.4 Memory Map ......................................................................................................... 4-2 4.5 I/O Registers Summary .........................................................................................4-3 5.1 RESETS ................................................................................................................5-1 5.1.1 Power-On Reset (POR) ................................................................................... 5-1 5.1.2 RESET Pin.......................................................................................................5-1 5.1.3 Low Voltage Reset (LVR) ...
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Paragraph Number CPU CORE AND INSTRUCTION SET 8.1 Registers ...............................................................................................................8-1 8.1.1 Accumulator (A) ...............................................................................................8-1 8.1.2 Index register (X)..............................................................................................8-2 8.1.3 Program counter (PC) ......................................................................................8-2 8.1.4 Stack pointer (SP) ............................................................................................8-2 8.1.5 Condition code register (CCR).........................................................................8-2 8.2 Instruction set ........................................................................................................8-3 8.2.1 Register/memory Instructions ...
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Paragraph Number 11.1 Maximum Ratings................................................................................................ 11-1 11.2 Thermal Characteristics ...................................................................................... 11-1 11.3 DC Electrical Characteristics............................................................................... 11-2 11.4 ADC Electrical Characteristics ............................................................................ 11-4 11.5 Control Timing ..................................................................................................... 11-5 MECHANICAL SPECIFICATIONS 12.1 40-Pin DIP Package (Case 711-03) .................................................................... 12-2 12.2 42-Pin SDIP ...
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LIST OF FIGURES Figure Number 1-1 MC68HC05SR3/ MC68HC705SR3 Block Diagram................................................ 1-3 2-1 Oscillator Connections............................................................................................ 2-3 2-2 Typical Oscillator Frequency for Selected External Resistor .................................. 2-4 2-3 Typical Oscillator Frequency for Wire-Strap Connection ........................................ 2-4 2-4 Pin Assignment for 40-pin PDIP ...
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THIS PAGE LEFT BLANK INTENTIONALLY Freescale vi TPG MC68HC05SR3 ...
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Table Number 1-1 Power-On Reset Delay Mask Option ...................................................................... 1-2 3-1 I/O Pin Functions .................................................................................................... 3-1 4-1 MC68HC05SR3/MC68HC705SR3 I/O Registers ................................................... 4-3 5-1 Reset/Interrupt Vector Addresses .......................................................................... 5-3 7-1 ADC Channel Assignments .................................................................................... 7-4 8-1 MUL instruction ...................................................................................................... 8-5 8-2 ...
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THIS PAGE LEFT BLANK INTENTIONALLY Freescale viii TPG MC68HC05SR3 ...
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GENERAL DESCRIPTION The MC68HC05SR3 HCMOS microcontroller is a member of the M68HC05 family of low-cost single-chip microcontrollers. This 8-bit microcontroller unit (MCU) contains on-chip oscillator, CPU, RAM, ROM, I/O, Timer, and Analog-to-Digital Converter. The MC68HC05SR3 is pin compatible with the ...
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Internal 100KΩ pull-up resistors on IRQ and RESET pins • Four channel 8-bit Analog to Digital Converter • Low Voltage Reset • Available in 40-pin PDIP, 42-pin SDIP and 44-pin QFP packages 1.2 Mask Options The following mask ...
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USER ROM/EPROM - 3840 BYTES SELF-CHECK/BOOTSTRAP ROM - 240 BYTES RAM - 192 BYTES 7 M68HC05 CPU IRQ RESET RESET CONDITION CODE REGISTER LOW VOLTAGE RESET 7-BIT PRESCALER POWER ...
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THIS PAGE LEFT BLANK INTENTIONALLY Freescale 1-4 GENERAL DESCRIPTION TPG MC68HC05SR3 ...
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PIN DESCRIPTIONS This section provides a description of the functional pins of the MC68HC05SR3 microcontroller. 2.1 Functional Pin Descriptions 40-pin PDIP 42-pin SDIP PIN NAME PIN No. PIN No. VDD 4 VSS 1 — VSS(INT) — VSS(EXT) — VPP 7 ...
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PDIP PIN NAME PIN No. 2 PA0-PA7 33-40 PB0-PB7 25-32 PC0-PC7 9-16 PD0-PD7 24-21, 20-17 AN0-AN3 24-21 IRQ2 18 VRH 19 VRL 20 2.2 OSC1 and OSC2 Connections The OSC1 and OSC2 pins are the connections for the on-chip ...
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The external oscillator clock frequency, f frequency MCU OSC1 10MΩ 25p (a) Crystal or ceramic resonator connections MCU OSC1 Unconnected (c) RC option 1 - external resistor 10% to 25% accurate Figure 2-1 Oscillator Connections 2.2.1 Crystal ...
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RC Oscillator Option 2 This configuration is intended to be the lowest cost option in applications where oscillator accuracy is not important. An internal constant current source and a capacitor have been integrated on-chip, connected between the OSC2 pin ...
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Pin Assignments RESET TIMER PD6/IRQ2 PD5/VRH PD4/VRL Figure 2-4 Pin Assignment for 40-pin PDIP MC68HC05SR3 VSS 1 40 PA7 2 39 PA6 IRQ 3 38 PA5 VDD 4 37 PA4 OSC1 5 36 PA3 OSC2 6 35 PA2 VPP ...
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VSS(EXT) Freescale 2-6 VSS(INT VSS(EXT RESET 3 40 IRQ 4 39 VDD 5 38 OSC1 6 37 OSC2 7 36 VPP 8 35 TIMER 9 34 PC0 10 33 PC1 11 32 PC2 12 31 ...
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INPUT/OUTPUT PORTS The MC68HC05SR3 has 32 bidirectional I/O lines, arranged as four 8-bit I/O ports (Port and D). The individual bits in these ports are programmable as either inputs or outputs under software control by the Data ...
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INTERNAL LATCHED OUTPUT MC68HC05 CONNECTIONS 3.1.2 Port Data Direction Registers Each port pin may be programmed as an input by clearing the corresponding bit in the DDR, or programmed as an output by setting the corresponding bit in the ...
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PD6 — IRQ2 The port pin PD6 is configured as IRQ2 by setting the IRQ2E bit in the MCR. The external interrupt IRQ2 behaves similar to IRQ except it is edge-triggered only. See Section 5.2.2.2 for details on the ...
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Freescale 3-4 V (volts worst case typical best case PB5-PB7 in low current mode worst case All ports typical ...
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Figure 3-5 Typical I 3.6 Programmable Pull-Up Devices Ports B, C, and D have 20KΩ pull-up resistors, which can be connected or disconnected, by setting appropriate bits in the Port Option Register (at $0A). 3.6.1 Port Option Register Address bit ...
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PCP — Port C Pull-up 1 (set) – The internal 20KΩ pull-up resistors are connected to the inputs of Port C. 0 (clear) – No pull-up resistor is connected to the inputs of Port C. 3 PBP — PB2:PB7 Pull-up ...
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MEMORY AND REGISTERS The MC68HC05SR3/MC68HC705SR3 has 8K-bytes of addressable memory, consisting of I/O registers, user ROM/EPROM, user RAM, and self-check/bootstrap ROM. Figure 4-1 shows the memory map for MC68HC05SR3/MC68HC705SR3 device. 4.1 I/O Registers The I/O, status and control registers are ...
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Memory Map Figure 4-1 shows the memory map for MC68HC05SR3/MC68HC705SR3 device. $0000 I/O 16 Bytes $000F $0010 4 User RAM 128 Bytes $008F $0090 Unused $00BF $00C0 Stack 64 Bytes $00FF $0100 Unused $0FFF $1000 User ROM/EPROM 3840 Bytes ...
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I/O Registers Summary Table 4-1 shows a summary of I/O registers for MC68HC05SR3/MC68HC705SR3 device. Table 4-1 MC68HC05SR3/MC68HC705SR3 I/O Registers Register Name Address Port A Data $00 Port B Data $01 Port C Data $02 Port D Data $03 Port ...
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THIS PAGE LEFT BLANK INTENTIONALLY Freescale 4-4 MEMORY AND REGISTERS TPG MC68HC05SR3 ...
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RESETS AND INTERRUPTS This section describes the reset and interrupt functions on the MCU. 5.1 RESETS The MC68HC05SR3 can be reset in three ways: • by initial power-on reset function, (POR), • active low input to the RESET ...
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Low Voltage Reset (LVR) When the LVR function is enabled, an internal reset is generated if the supply voltage, V below V . (See Section 11 for value of V LVR This LVR function is enabled by setting the ...
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UNSTACKING ORDER STACKING ORDER Figure 5-1 Interrupt Stacking Order Table 5-1 Reset/Interrupt Vector Addresses Register Flag Name — — — — — — — — External Interrupt 2 TCR TIF ...
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Y 5 Figure 5-2 Hardware Interrupt Processing Flowchart Freescale 5-4 From RESET Is I-bit Set IRQ External External Interrupt Interrupt ? Request Latch N Y IRQ2 External Interrupt ? N Y Timer Interrupt Keyboard Interrupt? N ...
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Maskable Hardware Interrupts If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts are masked. Clearing the I-bit allows interrupt processing to occur. Note: The internal interrupt latch is cleared in the first part of ...
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INTO BIT 100K IRQ 5 IRQ Wired ORed Interrupt signals IRQ Freescale 5-6 DD & & (a) Interrupt Function Diagram t ILIH t ILIL t ILIH (b) Interrupt Mode Diagram Figure ...
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External Interrupt 2 (IRQ2) The port pin PD6 is configured as IRQ2 by setting the IRQ2E bit in the MCR. The external interrupt IRQ2 behaves similar to IRQ except it is edge-triggered only. Address bit 7 Miscellaneous Control Register ...
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TIF — Timer Interrupt Flag 1 (set) – A timer interrupt (timer overflow) has occurred. 0 (clear) – A timer interrupt (timer overflow) has not occurred. The I-bit in the CCR must be cleared in order for the timer interrupt ...
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The KBIE bit in the Miscellaneous Control Register controls the master enable for the keyboard interrupts. Address bit 7 Miscellaneous Control Register $0C KBIE — KeyBoard Interrupt Enable 1 (set) – Keyboard interrupts master enabled. 0 (clear) – Keyboard interrupts ...
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THIS PAGE LEFT BLANK INTENTIONALLY Freescale 5-10 RESETS AND INTERRUPTS TPG MC68HC05SR3 ...
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This section describes the operation of the 8-bit count-down timer in the MC68HC05SR3. 6.1 Timer Overview The MC68HC05SR3 timer block diagram is shown in Figure 6-1. The timer contains a single 8-bit software programmable count-down counter with a 7-bit software ...
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Freescale 6-2 Timer Data Register ($08) 8 8-bit count-down timer counter 7-bit prescaler counter RST 8 Prescaler Overflow Detect ( MUX) Circuit Interrupt Circuit 8 TIF TIM TCEX TINE PRER PR2 Timer Control Register ($09) Clock ...
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Timer Control Register (TCR) The TCR enables the software to control the operation of the timer. Address bit 7 bit 6 $09 TIF TIM TIF — Timer Interrupt Flag 1 (set) – The timer has reached a count of ...
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PR2:PR0 These three bits enable the program to select the division ratio of the prescaler. On reset, these three bits are set to “100”, which corresponds to a division ratio of 16. 6 6.3 Timer Data Register (TDR) The TDR ...
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ANALOG TO DIGITAL CONVERTER The analog to digital converter system consists of a single 8-bit successive approximation converter and an 8-channel analog multiplexer. Four of the channels are available for analog inputs, and the other four channels are dedicated to ...
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ADC Operation As shown in Figure 7-1, the ADC consists of an analog multiplexer, an 8-bit digital to analog capacitor array, a comparator and a successive approximation register (SAR). There are eight options that can be selected by the ...
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ADC Status and Control Register (ADSCR) The ADSCR is a read/write register containing status and control bits for the ADC. Address bit 7 bit 6 $0E COCO ADRC ADON COCO — COnversion COmplete 1 (set) – An ADC conversion ...
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CH2 CH1 Using a port D pin as both an analog and digital input simultaneously is prohibited. When the ADC is enabled (ADON=1) and ...
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CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05SR3. 8.1 Registers The MCU contains five registers, as shown in the programming model of Figure ...
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Increasing memory address Unstack 8.1.2 Index register (X) The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area. ...
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Interrupt (I) When this bit is set, all maskable interrupts are masked interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. Negative (N) When set, this bit ...
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Register/memory Instructions Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump ...
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Operation Description Condition codes Source Form Table 8-2 Register/memory instructions Function Load A from memory LDA A6 Load X from memory LDX AE Store A in memory STA Store X in memory STX Add memory to A ADD AB Add ...
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Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear ...
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Table 8-5 Read/modify/write instructions Function Increment INC Decrement DEC Clear CLR Complement COM Negate (two’s complement) NEG Rotate left through carry ROL Rotate right through carry ROR Logical shift left LSL Logical shift right LSR Arithmetic shift right ASR Test ...
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Mnemonic INH ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS 8 BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET BSR CLC CLI CLR CMP Address mode abbreviations BSC ...
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Table 8-7 Instruction set (Continued) Mnemonic INH IMM DIR COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA ...
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Freescale 8-10 Table 8-8 M68HC05 opcode map CPU CORE AND INSTRUCTION SET TPG MC68HC05SR3 ...
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Addressing modes Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the ...
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Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte ...
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Relative The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are ...
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THIS PAGE LEFT BLANK INTENTIONALLY 8 Freescale 8-14 CPU CORE AND INSTRUCTION SET TPG MC68HC05SR3 ...
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LOW POWER MODES The MC68HC05SR3 has three low-power operating modes. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The flow of the STOP ...
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STOP Stop External Oscillator, Stop Internal Timer Clock, and Reset Start-Up Delay Stop Internal Processor Clock, Clear I-Bit in CCR External RESET External Hardware Interrupt? 9 Freescale 9 Reset External Oscillator, and Stabilization Delay End of ...
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SLOW Mode The SLOW mode function is controlled by the SM bit in the Miscellaneous Control Register. When the SM bit is set, the internal bus clock is divided by 16, resulting to a frequency equal to the oscillator ...
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THIS PAGE LEFT BLANK INTENTIONALLY 9 Freescale 9-4 LOW POWER MODES TPG MC68HC05SR3 ...
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OPERATING MODES The MC68HC05SR3/MC68HC705SR3 has two modes of operation: the User Mode and the Self-Check/Bootstrap Mode. Table 10-1 shows the conditions required for entering the two operating modes. RESET =2×V TST DD 10.1 User ...
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RESET + 1µF +5V 330 330 10 330 330 Freescale 10-2 MC68HC05SR3 4MHz OSC1 OUT OSC2 Crystal OSC RESET +5V 10K PB0 D1 PB4 PB1 D2 PB5 PB2 D3 PB6 PB3 D4 PB7 Figure 10-1 MC68HC05SR3 Self-Check Circuit ...
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D4 D3 Flashing 1=LED on, 0=LED off 10.3 Bootstrap Mode The Bootstrap mode is provided in the EPROM part (MC68HC705SR3 mean of ...
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THIS PAGE LEFT BLANK INTENTIONALLY 10 Freescale 10-4 OPERATING MODES TPG MC68HC05SR3 ...
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ELECTRICAL SPECIFICATIONS This section contains the electrical specifications for MC68HC05SR3. 11.1 Maximum Ratings (Voltages referenced RATINGS Supply Voltage Input Voltage V Pin PP Current Drain per pin excluding V DD Operating Temperature Standard Extended Storage Temperature ...
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DC Electrical Characteristics Table 11-1 DC Electrical Characteristics for 5V Operation =5.0Vdc ±10 CHARACTERISTICS Output voltage I = –10µA LOAD I = +10µA LOAD Output high voltage (I All Ports Output low voltage (I LOAD All ...
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Table 11-2 DC Electrical Characteristics for 3V Operation =3.0Vdc ±10 =0Vdc, temperature range=0 to 70° CHARACTERISTICS Output voltage I = –10µA LOAD I = +10µA LOAD Output high voltage (I =–0.8mA) LOAD All Ports Output low ...
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ADC Electrical Characteristics Table 11-3 ADC Electrical Characteristics for 5V and 3V Operation CHARACTERISTICS Resolution Absolute accuracy Conversion range Power-up time Conversion time Monotonicity Zero-input reading Full-scale reading Sample acquisition time Input capacitance Input leakage ...
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Control Timing Table 11-4 Control Timing for 5V Operation =5.0Vdc ±10 =0Vdc, temperature range=0 to 70° CHARACTERISTICS Frequency of operation RC oscillator Option Crystal option External clock option Internal operating frequency (f /2) OSC RC ...
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CHARACTERISTICS Frequency of operation RC oscillator Option Crystal option External clock option Internal operating frequency (f RC oscillator Crystal External clock Processor cycle time (1/f RC oscillator stabilization time Crystal oscillator start-up time (crystal oscillator) ...
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MECHANICAL SPECIFICATIONS This section provides the mechanical dimensions for the 40-pin DIP, 42-pin SDIP and 44-pin QFP packages for the MC68HC05SR3. MC68HC05SR3 MECHANICAL SPECIFICATIONS 12 12 TPG MOTOROLA 12-1 ...
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DIP Package (Case 711-03 12.2 42-Pin SDIP Package (Case 858-01) - -T- SEATING PLANE 0.25 (0.010) MOTOROLA 12 ...
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QFP Package (Case 824A-01 -A- L DETAIL -D- A 0.20 (0.008) C A-B M 0.05 (0.002) A-B S 0.20 (0.008) A -C- H SEATING G PLANE DATUM -H- ...
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THIS PAGE LEFT BLANK INTENTIONALLY 12 MOTOROLA 12-4 MECHANICAL SPECIFICATIONS TPG MC68HC05SR3 ...
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MC68HC705SR3 This appendix summarizes the differences between the MC68HC05SR3 and MC68HC705SR3. The same information can also be found in appropriate sections of the book. The MC68HC705SR3 is an EPROM version of the MC68HC05SR3. The 3840 bytes of user ROM in ...
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A.2 Modes of Operation The MC68HC705SR3 has two modes of operation – user mode and EPROM bootstrap mode. Table A-1 shows the conditions required to enter each mode on the rising edge of RESET. Table A-1 MC68HC705SR3 Operating Mode Entry ...
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A.4.1 EPROM Programming Programming boards are available from Freescale for programming the on-chip EPROM. Please contact your Freescale Representative. The Programming Control register (PCR) is provided for EPROM programming. The function of the EPROM depends on the device operating mode. ...
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CLR PCR LDX #$00 BSET 1,PCR LDA #$00 STA $1900,X BSET 0,PCR JSR DELAY CLR PCR A.5 Mask Option Register (MOR) The Mask Option Register (MOR) contains programmable EPROM bits to control mask options, and cannot be changed in User ...
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RC — Crystal Oscillator Option 1 (set) – Resistor option selected. 0 (clear) – Crystal option selected. A.6 Pin Assignments See Section 2.3 for pin assignments for the available packages. MC68HC05SR3 MC68HC705SR3 A TPG Freescale A-5 ...
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THIS PAGE LEFT BLANK INTENTIONALLY A Freescale A-6 MC68HC705SR3 TPG MC68HC05SR3 ...
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GENERAL DESCRIPTION PIN DESCRIPTIONS INPUT/OUTPUT PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS ANALOG TO DIGITAL CONVERTER CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS TIMER MC68HC705SR3 TPG ...
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GENERAL DESCRIPTION 2 PIN DESCRIPTIONS 3 INPUT/OUTPUT PORTS 4 MEMORY AND REGISTERS 5 RESETS AND INTERRUPTS 6 TIMER 7 ANALOG TO DIGITAL CONVERTER 8 CPU CORE AND INSTRUCTION SET 9 LOW POWER MODES 10 OPERATING MODES 11 ELECTRICAL SPECIFICATIONS ...
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