MC68HC11F1CFN4 Freescale Semiconductor, MC68HC11F1CFN4 Datasheet - Page 24
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MC68HC11F1CFN4
Manufacturer Part Number
MC68HC11F1CFN4
Description
IC MCU 512 EEPROM 4MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC11F1CFN4
Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
30
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC11F1CFN4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC11F1CFN4
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MC68HC11F1CFN4R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Bits 7:3 — See 6.2 EEPROM Registers, page 30. (These bits are implemented on the MC68HC11F1 only.)
NOCOP — COP System Disable
TEST1 — Factory Test
TILOP — Test Illegal Opcode
Bit 6 — Not implemented. Reads always return zero and writes have no effect.
OCCR — Output Condition Code Register to Timer Port
CBYP — Timer Divider Chain Bypass
DISR — Disable Resets from COP and Clock Monitor
FCM — Force Clock Monitor Failure
FCOP — Force COP Watchdog Failure
Bit 0 — Not implemented. Reads always return zero and writes have no effect.
24
CONFIG — EEPROM Mapping, COP, EEPROM Enables
RESET:
RESET
U = Unaffected by reset
These bits can only be written in test and bootstrap modes.
This test mode allows serial testing of all illegal opcodes without servicing an interrupt after each illegal
opcode is fetched.
In test and bootstrap modes, this bit is reset to one to inhibit clock monitor and COP resets. In normal
modes, DISR is reset to zero.
0 = COP enabled (forces reset on time-out)
1 = COP disabled (does not force reset on time-out)
0 = Normal operation (trap on illegal opcodes)
1 = Inhibit LIR when an illegal opcode is found
0 = Normal operation
1 = Condition code bits H, N, Z, V and C are driven on PA[7:3] to allow a test system to monitor
0 = Normal operation
1 = The 16-bit free-running timer is divided into two 8-bit halves and the prescaler is bypassed. The
0 = Normal operation
1 = COP and Clock Monitor failure do not generate a system reset
0 = Normal operation
1 = Generate an immediate clock monitor failure reset. Note that the CME bit in the OPTION register
0 = Normal operation
1 = Generate an immediate COP failure reset. Note that the NOCOP bit in the CONFIG register
CPU operation
system E clock drives both halves directly.
must also be set in order to force the reset.
must be cleared (COP enabled) in order to force the reset.
TILOP
Bit 7
Bit 7
EE3
U
0
EE2
U
6
6
0
0
Freescale Semiconductor, Inc.
For More Information On This Product,
OCCR
EE1
U
5
5
0
Go to: www.freescale.com
CBYP
EE0
U
4
4
0
DISR
3
1
1
—
3
NOCOP
FCM
U
2
2
0
FCOP
1
1
1
1
0
EEON
MC68HC11F1/FC0
Bit 0
MC68HC11FTS/D
Bit 0
U
0
0
$x03E
$x03F