MC68HC11F1CFN4 Freescale Semiconductor, MC68HC11F1CFN4 Datasheet - Page 55

• Manufacturer Part Number: MC68HC11F1CFN4
• Description: IC MCU 512 EEPROM 4MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CFN4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

11.3 A/D Registers
ADCTL — A/D Control/Status
CCF — Conversions Complete Flag
Bit 6 — Not implemented. Reads always return zero and writes have no effect.
SCAN — Continuous Scan Control
MULT — Multiple Channel/Single Channel Control
CD–CA — Channel Select D through A
MC68HC11F1/FC0
MC68HC11FTS/D
RESET:
I = Indeterminate value
A read-only status indicator, this bit is set when all four A/D result registers contain valid conversion re-
sults. Each time the ADCTL register is overwritten, this bit is automatically cleared to zero and a con-
version sequence is started. In the continuous mode, CCF is set at the end of the first conversion
sequence.
Refer to Table 24. When a multiple channel mode is selected (MULT = 1), the two least significant chan-
nel select bits (CB and CA) have no meaning and the CD and CC bits specify which group of four chan-
nels is to be converted.
0 = Do four conversions and stop
1 = Convert four channels in selected group continuously
0 = Convert single channel selected
1 = Convert four channels in selected group
NOTES:
Channel Select Control Bits
1. Used for factory testing.
CCF
Bit 7
I
CD:CC:CB:CA
10XX
0000
0001
0010
0011
0100
0101
0110
0111
1100
1101
1110
1111
6
0
0
Freescale Semiconductor, Inc.
Table 24 A/D Converter Channel Assignments
For More Information On This Product,
SCAN
5
I
Go to: www.freescale.com
Channel Signal
MULT
Reserved
4
Reserved
I
(V
V
V
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
RH
RH
RL
)/2
1
1
1
1
CD
3
I
Result in ADRx if MULT = 1
CC
2
I
ADR1–ADR4
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
CB
1
I
Bit 0
CA
I
$x030
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