MCF5307FT66B Freescale Semiconductor, MCF5307FT66B Datasheet - Page 321
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MCF5307FT66B
Manufacturer Part Number
MCF5307FT66B
Description
IC MPU 32BIT COLDF 66MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT66B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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14.3.6 UART Receiver Buffers (URBn)
The receiver buffers contain one serial shift register and three receiver holding registers,
which act as a FIFO. RxD is connected to the serial shift register. The CPU reads from the
top of the stack while the receiver shifts and updates from the bottom when the shift register
is full (see Figure 14-20). RB contains the character in the receiver.
14.3.7 UART Transmitter Buffers (UTBn)
The transmitter buffers consist of the transmitter holding register and the transmitter shift
register. The holding register accepts characters from the bus master if channel’s
USRn[TxRDY] is set. A write to the transmitter buffer clears TxRDY, inhibiting any more
characters until the shift register can accept more data. When the shift register is empty, it
checks if the holding register has a valid character to be sent (TxRDY = 0). If there is a valid
character, the shift register loads it and sets USRn[TxRDY] again. Writes to the transmitter
buffer when the channel’s TxRDY = 0 and when the transmitter is disabled have no effect
on the transmitter buffer.
Figure 14-8 shows UTB0. TB contains the character in the transmitter buffer.
Bits
1–0
Address
Reset
Field
R/W
Value
00
01
10
11
NO ACTION TAKEN
RECEIVER ENABLE
RECEIVER DISABLE
7
Command
Table 14-6. UCRn Field Descriptions (Continued)
—
Figure 14-7. UART Receiver Buffer (URB0)
Freescale Semiconductor, Inc.
For More Information On This Product,
Causes the receiver to stay in its current mode. If the receiver is enabled, it
remains enabled; if disabled, it remains disabled.
If the UART module is not in multidrop mode (UMR1n[PM] ≠ 11),
ENABLE
If the receiver is already enabled, this command has no effect.
Disables the receiver immediately. Any character being received is lost. The
command does not affect receiver status bits or other control registers. If the
UART module is programmed for local loop-back or multidrop mode, the receiver
operates even though this command is selected. If the receiver is already
disabled, the command has no effect.
Reserved, do not use.
RC (This field selects a single command)
Chapter 14. UART Modules
Go to: www.freescale.com
enables the channel's receiver and forces it into search-for-start-bit state.
MBAR + 0x1CC,0x20C
0000_0000
Read only
RB
Description
Register Descriptions
RECEIVER
0
14-11
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