MC68HC908JL8CDW Freescale Semiconductor, MC68HC908JL8CDW Datasheet - Page 112
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MC68HC908JL8CDW
Manufacturer Part Number
MC68HC908JL8CDW
Description
IC MCU 8K FLASH 8MHZ 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JL8CDWER.pdf
(212 pages)
Specifications of MC68HC908JL8CDW
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Part Number:
MC68HC908JL8CDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
MC68HC908JL8CDWE
Manufacturer:
FREESCALE
Quantity:
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Timer Interface Module (TIM)
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel
0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0
(TSCR0) controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. (See
8.5 Interrupts
The following TIM sources can generate interrupt requests:
8.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
8.6.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not
accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait
mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
8.6.2 Stop Mode
The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect
register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode
after an external interrupt.
112
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
•
•
TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control
register.
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1.
CHxF and CHxIE are in the TIM channel x status and control register.
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
8.9.4 TIM Channel Status and Control
Registers.)
Freescale Semiconductor
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