MC68HC908JL8CDW Freescale Semiconductor, MC68HC908JL8CDW Datasheet - Page 164
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MC68HC908JL8CDW
Manufacturer Part Number
MC68HC908JL8CDW
Description
IC MCU 8K FLASH 8MHZ 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JL8CDWER.pdf
(212 pages)
Specifications of MC68HC908JL8CDW
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908JL8CDW
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Part Number:
MC68HC908JL8CDWE
Manufacturer:
FREESCALE
Quantity:
20 000
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External Interrupt (IRQ)
The vector fetch or software clear may occur before or after the interrupt pin returns to logic one. As long
as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
12.3.1 IRQ Pin
A logic zero on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear,
or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set,
both of the following actions must occur to clear IRQ:
164
Addr.
$001D
IRQPUD
IRQ
IRQ Status and Control
Register Name
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests. (See
Control.)
DECODER
VECTOR
FETCH
MC68HC908JL8/JK8 • MC68HC08JL8/JK8 • MC68HC908KL8 Data Sheet, Rev. 3.1
RESET
ACK
V
DD
INTERNAL
PULLUP
DEVICE
(INTSCR)
Register
Reset:
Read:
Write:
Figure 12-1. IRQ Module Block Diagram
Figure 12-2. IRQ I/O Register Summary
V
MODE
DD
Bit 7
D
0
0
CK
CLR
Q
= Unimplemented
6
0
0
NOTE
5
0
0
IMASK
SYNCHRONIZER
4
0
0
VOLTAGE
DETECT
HIGH
IRQF
3
0
5.5 Exception
ACK
2
0
0
IRQF
Freescale Semiconductor
IMASK
1
0
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
MODE
Bit 0
0
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