COP8SCR9IMT8 National Semiconductor, COP8SCR9IMT8 Datasheet - Page 69

IC MCU EEPROM 8BIT 32K 48-TSSOP

COP8SCR9IMT8

Manufacturer Part Number
COP8SCR9IMT8
Description
IC MCU EEPROM 8BIT 32K 48-TSSOP
Manufacturer
National Semiconductor
Series
COP8™ 8Sr
Datasheet

Specifications of COP8SCR9IMT8

Core Processor
COP8
Core Size
8-Bit
Speed
20MHz
Connectivity
Microwire/Plus (SPI), UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
*COP8SCR9IMT8
19.0 Instruction Set
19.7 INSTRUCTION EXECUTION TIME
Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
Note 17: =
ADD
ADC
SUBC
AND
OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
>
X A, (Note 17)
LD A, (Note 17)
LD B,Imm
LD B,Imm
LD Mem,Imm
LD Reg,Imm
IFEQ MD,Imm
Memory location addressed by B or X or directly.
RPND
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Direct
1/1
1/1
2/2
[B]
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
1/3
3/4
3/4
3/4
(Continued)
Register
1/1
Indirect
1/3
1/3
[X]
Immed.
Memory Transfer Instructions
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
Direct
2/3
2/3
3/3
2/3
3/3
Immed.
2/2
1/1
2/2
69
Instructions Using A & C
Transfer of Control Instructions
[B+, B−]
Auto Incr. & Decr.
1/2
1/2
2/2
Register Indirect
CLRA
INCA
DECA
LAID
DCORA
RRCA
RLCA
SWAPA
SC
RC
IFC
IFNC
PUSHA
POPA
ANDSZ
JMPL
JMP
JP
JSRL
JSR
JSRB
JID
VIS
RET
RETSK
RETI
INTR
NOP
[X+, X−]
1/3
1/3
(If B
(If B
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/3
1/3
2/2
3/4
2/3
1/3
3/5
2/5
2/5
1/3
1/5
1/5
1/5
1/5
1/7
1/1
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