MC68HC908GZ8MFA Freescale Semiconductor, MC68HC908GZ8MFA Datasheet - Page 167
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MC68HC908GZ8MFA
Manufacturer Part Number
MC68HC908GZ8MFA
Description
IC MCU 8K FLASH 8MHZ CAN 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GZ8CFJER.pdf
(314 pages)
Specifications of MC68HC908GZ8MFA
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908GZ8MFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits
13.7 Port E
Port E is a 6-bit special-function port that shares two of its pins with the enhanced serial communications
interface (ESCI) module.
13.7.1 Port E Data Register
The port E data register contains a data latch for each of the six port E pins.
PTE5-PTE0 — Port E Data Bits
RxD — SCI Receive Data Input
TxD — SCI Transmit Data Output
13.7.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a
logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the
output buffer.
Freescale Semiconductor
These writable bits are software programmable to enable pullup devices on an input port bit.
These read/write bits are software-programmable. Data direction of each port E pin is under the control
of the corresponding bit in data direction register E. Reset has no effect on port E data.
The PTE1/RxD pin is the receive data input for the ESCI module. When the enable SCI bit, ENSCI, is
clear, the ESCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
Chapter 15 Enhanced Serial Communications Interface (ESCI)
The PTE0/TxD pin is the transmit data output for the ESCI module. When the enable SCI bit, ENSCI,
is clear, the ESCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 15 Enhanced Serial Communications Interface (ESCI)
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
Alternative
Function:
Address:
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the ESCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See
Reset:
Read:
Write:
$0008
Bit 7
0
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
= Unimplemented
Figure 13-17. Port E Data Register (PTE)
6
0
PTE5
5
Table
NOTE
Unaffected by reset
PTE4
13-6.
4
PTE3
3
Module.
Module.
PTE2
2
PTE1
RxD
1
PTE0
Bit 0
TxD
Port E
167
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