MC68HC908GZ8MFA Freescale Semiconductor, MC68HC908GZ8MFA Datasheet - Page 271

• Manufacturer Part Number: MC68HC908GZ8MFA
• Description: IC MCU 8K FLASH 8MHZ CAN 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GZ8MFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 20
Development Support
20.1 Introduction
This section describes the break module, the monitor read-only memory (MON), and the monitor mode
entry methods.
20.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
Features of the break module include:
20.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU
to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to
$FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
When a CPU generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the microcontroller unit (MCU) to normal operation.
Figure 20-1
Figure 20-2
Freescale Semiconductor
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Accessible input/output (I/O) registers during the break Interrupt
Central processor unit (CPU) generated break interrupts
Software-generated break interrupts
Computer operating properly (COP) disabling during break interrupts
A CPU generated address (the address in the program counter) matches the contents of the break
address registers.
Software writes a logic 1 to the BRKA bit in the break status and control register.
shows the structure of the break module.
provides a summary of the I/O registers.
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