MC68HC908GR16VFJ Freescale Semiconductor, MC68HC908GR16VFJ Datasheet - Page 234
MC68HC908GR16VFJ
Manufacturer Part Number
MC68HC908GR16VFJ
Description
IC MCU 16K FLASH 8MHZ SPI 32LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68908GR16CFJE.pdf
(276 pages)
Specifications of MC68HC908GR16VFJ
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MC68HC908GR16VFJ
Manufacturer:
Freescale Semiconductor
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Timer Interface Module (TIM)
CHxF — Channel x Flag Bit
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
234
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIM counter registers matches the value in the TIM channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x
status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an
interrupt request cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE
bit.
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1
channel 0 and TIM2 channel 0 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. See
Reset clears the MSxA bit.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
Address: T1SC1, $0028 and T2SC1, $0033
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
Reset:
Read:
Write:
Figure 18-11. TIM Channel 1 Status and Control Register (TSC1)
CH1F
Bit 7
0
0
CH1IE
6
0
Table
MC68HC908GR16 Data Sheet, Rev. 5.0
18-3.
5
0
0
NOTE
MS1A
4
0
ELS1B
3
0
ELS1A
2
0
TOV1
1
0
Freescale Semiconductor
CH1MAX
Bit 0
0
Table
18-3.
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