MC68HC908JB16JDW Freescale Semiconductor, MC68HC908JB16JDW Datasheet - Page 264

• Manufacturer Part Number: MC68HC908JB16JDW
• Description: IC MCU 16K FLASH 6MHZ USB 20SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908JB16JDW

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 6MHz
• Connectivity: SCI, USB
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Input/Output (I/O) Ports
Technical Data
264
* DDRA7 bit is reset by POR or LVI reset only.
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
Data Direction Register C
Data Direction Register D
Data Direction Register A
Register Name
Port C Data Register
Port D Data Register
Port A Data Register
Port E Data Register
NOTE:
Reserved
Reserved
(DDRC)
(DDRD)
(DDRA)
(PTA)
(PTC)
(PTD)
(PTE)
Connect any unused I/O pins to an appropriate logic level, either V
V
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
SS
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Figure 14-1. I/O Port Register Summary
. Although the I/O ports do not require termination for proper
DDRA7
PTA7
Bit 7
0*
R
R
0
0
0
0
0
0
0
Input/Output (I/O) Ports
= Unimplemented
DDRA6
PTA6
R
R
6
0
0
0
0
0
0
0
0
DDRA5
DDRD5
PTA5
PTD5
R
R
5
0
0
0
0
0
0
Unaffected by reset
Unaffected by reset
Unaffected by reset
DDRA4
DDRD4
Unaffected by reset
PTA4
PTD4
PTE4
R
R
4
0
0
0
0
0
DDRA3
DDRD3
PTA3
PTD3
PTE3
R
R
R
3
0
0
0
0
0
MC68HC908JB16
= Reserved
DDRD2
DDRA2
PTA2
PTD2
PTE2
Freescale Semiconductor
R
R
0
0
0
0
0
2
DDRC1
DDRD1
DDRA1
PTA1
PTC1
PTD1
PTE1
R
R
1
0
0
0
—
DDRC0
DDRD0
Rev. 1.1
DDRA0
PTA0
PTC0
PTD0
PTE0
Bit 0
DD
R
R
0
0
0
or