MC9S08GB60CFU Freescale Semiconductor, MC9S08GB60CFU Datasheet - Page 131

• Manufacturer Part Number: MC9S08GB60CFU
• Description: IC MCU 60K FLASH 20MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GB60CFU

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.4.5
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of
program memory after the opcode (high byte first).
8.4.6
Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair and
two that use the stack pointer as the base reference.
8.4.6.1
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction.
8.4.6.2
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction. The index register pair is then incremented
(H:X = H:X + $0001) after the operand has been fetched. This addressing mode is only used for MOV and
CBEQ instructions.
8.4.6.3
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
8.4.6.4
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
The index register pair is then incremented (H:X = H:X + $0001) after the operand has been fetched. This
addressing mode is used only for the CBEQ instruction.
8.4.6.5
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
8.4.6.6
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.
Freescale Semiconductor
Extended Addressing Mode (EXT)
Indexed Addressing Mode
Indexed, No Offset (IX)
Indexed, No Offset with Post Increment (IX+)
Indexed, 8-Bit Offset (IX1)
Indexed, 8-Bit Offset with Post Increment (IX1+)
Indexed, 16-Bit Offset (IX2)
SP-Relative, 8-Bit Offset (SP1)
MC9S08GB/GT Data Sheet, Rev. 2.3
Addressing Modes
131