MC9S08GB60CFU Freescale Semiconductor, MC9S08GB60CFU Datasheet - Page 179

• Manufacturer Part Number: MC9S08GB60CFU
• Description: IC MCU 60K FLASH 20MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GB60CFU

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

SCISWAI — SCI Stops in Wait Mode
RSRC — Receiver Source Select
M — 9-Bit or 8-Bit Mode Select
WAKE — Receiver Wakeup Method Select
ILT — Idle Line Type Select
PE — Parity Enable
PT — Parity Type
Freescale Semiconductor
This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver input
is internally connected to the TxD1 pin and RSRC determines whether this connection is also
connected to the transmitter output.
Refer to
Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward
the 10 or 11 bit times of the logic high level by the idle line detection logic. Refer to
“Idle-Line
Enables hardware parity generation and checking. When parity is enabled, the most significant bit
(MSB) of the data character (eighth or ninth data bit) is treated as the parity bit.
Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total
number of 1s in the data character, including the parity bit, is odd. Even parity means the total number
of 1s in the data character, including the parity bit, is even.
1 = SCI clocks freeze while CPU is in wait mode.
0 = SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes
1 = Single-wire SCI mode where the TxD1 pin is connected to the transmitter output and receiver
0 = Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the
1 = Receiver and transmitter use 9-bit data characters
0 = Normal — start + 8 data bits (LSB first) + stop.
1 = Address-mark wakeup.
0 = Idle-line wakeup.
1 = Idle character bit count starts after stop bit.
0 = Idle character bit count starts after start bit.
1 = Parity enabled.
0 = No hardware parity generation or checking.
1 = Odd parity.
0 = Even parity.
up the CPU.
input.
RxD1 or TxD1 pins.
start + 8 data bits (LSB first) + 9th data bit + stop.
Section 11.6.3, “Receiver Wakeup
Wakeup,”
for more information.
MC9S08GB/GT Data Sheet, Rev. 2.3
Operation,”
for more information.
SCI Registers and Control Bits
Section 11.6.3.1,
179