C8051F019 Silicon Laboratories Inc, C8051F019 Datasheet - Page 125

• Manufacturer Part Number: C8051F019
• Description: IC 8051 MCU 16K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F018r

Specifications of C8051F019

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

125
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
C8051F018
C8051F019
R/W
TF1
Bit7
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is
automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is
automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can
be cleared by software but is automatically cleared when the CPU vectors to the External
Interrupt 1 service routine if IT1 = 1. This flag is the inverse of the /INT1 input signal’s
logic level when IT1 = 0.
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 signal will detect falling edge or active-low
level-sensitive interrupts.
0: /INT1 is level triggered.
1: /INT1 is edge triggered.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can
be cleared by software but is automatically cleared when the CPU vectors to the External
Interrupt 0 service routine if IT0 = 1. This flag is the inverse of the /INT0 input signal’s
logic level when IT0 = 0.
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 signal will detect falling edge or active-low
level-sensitive interrupts.
0: /INT0 is level triggered.
1: /INT0 is edge triggered.
IE1: External Interrupt 1.
IE0: External Interrupt 0.
TR1
R/W
Bit6
R/W
TF0
Bit5
Figure 17.4. TCON: Timer Control Register
R/W
TR0
Bit4
Rev. 1.2
R/W
IE1
Bit3
R/W
Bit2
IT1
R/W
Bit1
IE0
(bit addressable)
R/W
IT0
Bit0
SFR Address:
Reset Value
00000000
0x88