C8051F350 Silicon Laboratories Inc, C8051F350 Datasheet - Page 81

• Manufacturer Part Number: C8051F350
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F350

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x24b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Data Bus Width: 8 bit
• Data Rom Size: 128 B
• On-chip Adc: 10 bit
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.4 mm
• Length: 7 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Width: 7 mm
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

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10.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The C8051F35x family has a superset of all the peripherals included with a standard 8051. See Sec-
tion
includes on-chip debug hardware which interfaces directly with the analog and digital subsystems, provid-
ing a complete data acquisition or control-system solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram).
The CIP-51 core includes the following features:
Fully Compatible with MCS-51 Instruction Set
50 MIPS Peak Throughput
256 Bytes of Internal RAM
Extended Interrupt Handler
“1. System
CIP-51 Microcontroller
Overview” on page
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
PROGRAM COUNTER (PC)
CONTROL
Figure 10.1. CIP-51 Block Diagram
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
13
BUFFER
for more information about the available peripherals. The CIP-51
TMP1
PIPELINE
ALU
Rev. 0.4
TMP2
DATA BUS
DATA BUS
D8
D8
D8
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-
-
-
A16
D8
D8
D8
D8
Reset Input
Power Management Modes
Integrated Debug Logic
Program and Data Memory Security
B REGISTER
REGISTER
ADDRESS
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
MEMORY
SRAM
SFR
BUS
C8051F350/1/2/3
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
81