C8051F351 Silicon Laboratories Inc, C8051F351 Datasheet - Page 192

• Manufacturer Part Number: C8051F351
• Description: IC 8051 MCU 8K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F351

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x24b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F350/1/2/3
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“18.1. Priority Crossbar Decoder” on page 135
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see Figure 22.6).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see Figure 12.5). Setting GATE0 to ‘1’ allows
the timer to be controlled by the external input signal /INT0 (see
tions” on page
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
Figure 12.5).
22.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
192
/INT0
T0
Crossbar
101), facilitating pulse width measurements.
Pre-scaled Clock
SYSCLK
IN0PL
GATE0
Figure 22.1. T0 Mode 0 Block Diagram
TR0
X = Don't Care
XOR
0
1
1
1
TR0
0
1
M
T
H
3
GATE0
M
T
3
L
CKCON
M
T
H
2
X
0
1
1
T
M
2
L
0
1
M
T
1
T
M
0
S
C
A
1
for information on selecting and configuring external I/O
Rev. 0.4
S
C
A
0
G
A
T
E
1
/INT0
C
T
1
/
M
T
1
1
TMOD
X
X
0
1
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
Counter/Timer
(5 bits)
TL0
Section “12.4. Interrupt Register Descrip-
N
P
1
L
I
Disabled
Disabled
N
S
1
L
2
Enabled
Enabled
I
INT01CF
N
S
1
L
1
I
N
S
1
L
0
I
N
P
0
L
(8 bits)
I
TH0
N
S
0
L
2
I
N
S
0
L
1
I
N
S
0
L
0
I
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Section