MC68HC908SR12CB Freescale Semiconductor, MC68HC908SR12CB Datasheet - Page 302

• Manufacturer Part Number: MC68HC908SR12CB
• Description: IC MCU 12K FLASH 8MHZ 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908SR12CB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 29
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Multi-Master IIC Interface (MMIIC)
Data Sheet
302
MMTXAK — MMIIC Transmit Acknowledge Enable
REPSEN — Repeated Start Enable
MMCRCBYTE — MMIIC CRC Byte
This bit is set to disable the MMIIC from sending out an acknowledge
signal to the bus at the 9th clock bit after receiving 8 data bits. When
MMTXAK is cleared, an acknowledge signal will be sent at the 9th
clock bit. Reset clears this bit.
This bit is set to enable repeated START signal to be generated when
in master mode transfer (MMAST = 1). The REPSEN bit is cleared by
hardware after the completion of repeated START signal or when the
MMAST bit is cleared. Reset clears this bit.
In receive mode, this bit is set by software to indicate that the next
receiving byte will be the packet error checking (PEC) data.
In master receive mode, after completion of CRC generation on the
received PEC data, an acknowledge signal is sent if MMTXAK = 0; no
acknowledge is sent If MMTXAK = 1.
In slave receive mode, no acknowledge signal is sent if a CRC error
is detected on the received PEC data. If no CRC error is detected, an
acknowledge signal is sent if MMTXAK = 0; no acknowledge is sent If
MMTXAK = 1.
Under normal operation, the user software should clear MMTXAK bit
before setting MMCRCBYTE bit to ensure that an acknowledge signal
is sent when no CRC error is detected.
The MMCRCBYTE bit should not be set in transmit mode. This bit is
cleared by the next START signal. Reset also clears this bit.
1 = MMIIC does not send acknowledge signals at 9th clock bit
0 = MMIIC sends acknowledge signal at 9th clock bit
1 = Repeated START signal will be generated if MMAST bit is set
0 = No repeated START signal will be generated
1 = Next receiving byte is the packet error checking (PEC) data
0 = Next receiving byte is not PEC data
Multi-Master IIC Interface (MMIIC)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor