C8051F133 Silicon Laboratories Inc, C8051F133 Datasheet - Page 21
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C8051F133
Manufacturer Part Number
C8051F133
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F133
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit to 12 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
336-1150
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F133
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F133-GQ
Manufacturer:
SILICON
Quantity:
5
Company:
Part Number:
C8051F133-GQ
Manufacturer:
SiliconL
Quantity:
570
Company:
Part Number:
C8051F133-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F133-GQR
Manufacturer:
ST
Quantity:
101
Company:
Part Number:
C8051F133-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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MONEN
VREFD
XTAL1
XTAL2
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
DGND
DGND
DGND
AGND
AGND
VREF
DAC1
DAC0
CP0+
CP1+
CP0-
CP1-
VDD
VDD
VDD
TCK
TMS
TDO
AV+
AV+
RST
TDI
CP0
Analog Power
Digital Power
M
A
U
X
Calibrated Internal
External Oscillator
Monitor
VDD
Oscillator
JTAG
CP1
Logic
Circuit
(12-Bit)
(12-Bit)
VREF
DAC1
DAC0
SENSOR
TEMP
Circuitry
Prog
Gain
PLL
Boundary Scan
WDT
Debug HW
Figure 1.1. C8051F120/124 Block Diagram
100 ksps
(12-Bit)
System
Clock
ADC
Reset
C
o
8
0
5
1
e
r
External Data
Memory Bus
64x4 byte
256 byte
SFR Bus
FLASH
128 kB
XRAM
cache
RAM
8 kB
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
Timers 0,
Crossbar
SPI Bus
Timer 3/
Port I/O
Latches
Config.
UART0
UART1
SMBus
P0, P1,
Config.
P2, P3
1, 2, 4
PCA
RTC
Address Bus
Bus Control
Data Bus
C8051F130/1/2/3
ADC
500 ksps
(8-Bit)
C
A
D
T
L
d
d
a
a
r
t
C
R
O
S
S
B
A
R
P4 Latch
P5 Latch
P6 Latch
P7 Latch
Prog
Gain
P0
Drv
P1
Drv
P2
Drv
P3
Drv
M
U
A
X
8:1
DRV
DRV
DRV
DRV
P4
P5
P6
P7
P0.0
P0.7
P1.0/AIN2.0
P1.7/AIN2.7
P2.0
P2.7
P3.0
P3.7
VREF2
P4.0
P4.4
P4.5/ALE
P4.6/RD
P4.7/WR
P5.0/A8
P5.7/A15
P6.0/A0
P6.7/A7
P7.0/D0
P7.7/D7
21
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