C8051F133 Silicon Laboratories Inc, C8051F133 Datasheet - Page 263
C8051F133
Manufacturer Part Number
C8051F133
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F133
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit to 12 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
336-1150
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19.3.3. Slave Transmitter Mode
Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives
a START followed by data byte containing the slave address and direction bit. If the received slave address
matches the address held in register SMB0ADR, the SMBus0 interface generates an ACK. SMBus0 will
also ACK if the general call address (0x00) is received and the General Call Address Enable bit
(SMB0ADR.0) is set to logic 1. In this case the data direction bit (R/W) will be logic 1 to indicate a "READ"
operation. The SMBus0 interface receives the clock on SCL and transmits one or more bytes of serial
data, waiting for an ACK from the master after each byte. SMBus0 exits slave mode after receiving a
STOP condition from the master.
19.3.4. Slave Receiver Mode
Serial data is received on SDA while the serial clock is received on SCL. The SMBus0 interface receives a
START followed by data byte containing the slave address and direction bit. If the received slave address
matches the address held in register SMB0ADR, the interface generates an ACK. SMBus0 will also ACK if
the general call address (0x00) is received and the General Call Address Enable bit (SMB0ADR.0) is set to
logic 1. In this case the data direction bit (R/W) will be logic 0 to indicate a "WRITE" operation. The
SMBus0 interface receives one or more bytes of serial data; after each byte is received, the interface
transmits an ACK or NACK depending on the state of the AA bit in SMB0CN. SMBus0 exits Slave Receiver
Mode after receiving a STOP condition from the master.
S
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 19.6. Typical Slave Transmitter Sequence
Figure 19.7. Typical Slave Receiver Sequence
SLA
SLA
Interrupt
W
R
Interrupt
A
A
Data Byte
Data Byte
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
Interrupt
Interrupt
A
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Data Byte
Data Byte
C8051F130/1/2/3
Interrupt
Interrupt
A
N
Interrupt
Interrupt
P
P
263
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