C8051F133 Silicon Laboratories Inc, C8051F133 Datasheet - Page 40
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C8051F133
Manufacturer Part Number
C8051F133
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F13xr
Specifications of C8051F133
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit to 12 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Other names
336-1150
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Part Number
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Quantity
Price
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Part Number:
C8051F133
Manufacturer:
Silicon Laboratories Inc
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Part Number:
C8051F133-GQ
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SILICON
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C8051F133-GQ
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SiliconL
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Company:
Part Number:
C8051F133-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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Part Number:
C8051F133-GQR
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ST
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Part Number:
C8051F133-GQR
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Silicon Laboratories Inc
Quantity:
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C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7)
–40 to +85 °C, 50 MHz System Clock unless otherwise specified.
40
Analog Supply Voltage
Analog Supply Current
Analog Supply Current with
analog sub-systems inactive
Analog-to-Digital Supply
Delta (|V
Digital Supply Voltage
Digital Supply Current with
CPU active
Digital Supply Current with
CPU inactive (not accessing
Flash)
Digital Supply Current (shut-
down)
Digital Supply RAM Data
Retention Voltage
SYSCLK (System Clock)
Specified Operating
Temperature Range
Notes:
1. Analog Supply AV+ must be greater than 1 V for
2. SYSCLK is the internal device clock. For operational speeds in excess of 30 MHz, SYSCLK must be derived
3. SYSCLK must be at least 32 kHz to enable debugging.
from the phase-locked loop (PLL).
DD
Parameter
– AV+|)
1
2,3
Internal REF, ADC, DAC, Com-
parators all active
Internal REF, ADC, DAC, Com-
parators all disabled, oscillator
disabled
V
V
V
V
V
V
Oscillator not running
DD
DD
DD
DD
DD
DD
= 3.0 V, Clock = 50 MHz
= 3.0 V, Clock = 1 MHz
= 3.0 V, Clock = 32 kHz
= 3.0 V, Clock = 50 MHz
= 3.0 V, Clock = 1 MHz
= 3.0 V, Clock = 32 kHz
Conditions
Rev. 1.4
V
DD
monitor to operate.
Min
–40
2.7
2.7
—
—
—
—
—
—
—
0
Typ
3.0
1.7
0.2
3.0
0.4
0.4
1.5
35
33
27
15
—
—
—
1
Max
+85
3.6
0.5
3.6
50
—
—
—
—
—
—
Units
MHz
mA
mA
mA
mA
mA
µA
µA
µA
µA
°C
V
V
V
V
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