C8051F330D Silicon Laboratories Inc, C8051F330D Datasheet - Page 35

• Manufacturer Part Number: C8051F330D
• Description: IC 8051 MCU 8K FLASH 20DIP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F33xr

Specifications of C8051F330D

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 336-1155

5.
The ADC0 subsystem for the C8051F330 and C8051F330D consists of two analog multiplexers (referred
to collectively as AMUX0) with 16 total input selections, and a 200 ksps, 10-bit successive-approximation-
register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data con-
version modes, and window detector are all configurable under software control via the Special Function
Registers shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be
configured to measure Ports0-1, the Temperature Sensor output, or
The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set
to logic 1. The ADC0 subsystem is in low power shutdown when this bit is logic 0.
Sensor
Temp
VREF
GND
10-Bit ADC (ADC0, C8051F330 and C8051F330D only)
P0.0
P0.7
P1.0
P1.7
VDD
P0.0
P0.7
P1.0
P1.7
18-to-1
18-to-1
AMUX
AMUX
Figure 5.1. ADC0 Functional Block Diagram
AMX0P
AMX0N
C8051F330/1, C8051F330D
Rev. 1.2
(+)
(-)
ADC0CF
ADC
10-Bit
VDD
SAR
V
ADC0GTH ADC0GTL
ADC0LTH
DD with respect to Ports0-1 or GND.
ADC0CN
ADC0LTL
Conversion
Start
000
001
010
011
100
101
32
AD0WINT
Compare
Window
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
Logic
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