C8051F330D Silicon Laboratories Inc, C8051F330D Datasheet - Page 90
C8051F330D
Manufacturer Part Number
C8051F330D
Description
IC 8051 MCU 8K FLASH 20DIP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Datasheet
1.C8051F330R.pdf
(208 pages)
Specifications of C8051F330D
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
336-1155
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C8051F330/1, C8051F330D
10.1. Power-On Reset
During power-up, the device is held in a reset state and the /RST pin is driven low until
V
increases (
power-on and
cause the device to be released from reset before
1 ms, the power-on reset delay (T
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The
power-on reset.
90
RST
. A delay occurs before the device is released from reset; the delay decreases as the
V
DD ramp time is defined as how fast
V
DD monitor reset timing. The maximum
Logic HIGH
Logic LOW
2.70
2.55
2.0
1.0
Figure 10.2. Power-On and
/RST
V
PORDelay
RST
Power-On
Reset
) is typically less than 0.3 ms.
T
PORDelay
Rev. 1.2
V
V
DD reaches the V
V
DD ramps from 0 V to V
DD Monitor Reset Timing
V
DD ramp time is 1 ms; slower ramp times may
Monitor
Reset
VDD
V
RST
DD monitor is disabled following a
level. For ramp times less than
RST
). Figure 10.2. plots the
VDD
V
DD settles above
V
t
DD ramp time
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